采用无负载架构的1 v 100MS/s 8位CMOS开关运放流水线ADC

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705347

Ying Wu, V. Cheung, H. Luong

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引用次数: 16

摘要

采用多相开关运放(SO)技术实现了1V、8位双模ADC。采用无负载流水线ADC架构和快速唤醒双输入双输出可切换运放，ADC实现了100MS/s的转换速率，这是在1v电源下报道的最快的操作速度，可与许多高压开关电容(SC) ADC相媲美。该ADC采用0.18 μ m CMOS工艺实现，峰值信噪比为45dB, SFDR为52.6dB，功耗仅为30mW

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A 1-V 100MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture

A 1V, 8-bit dual-mode ADC is realized using multi-phase switched-opamp (SO) technique. Employing a proposed loading-free pipelined ADC architecture and a fast-wake-up dual-input-dual-output switchable opamp, the ADC achieves 100MS/s conversion rate, which is the fastest operation speed reported at 1-V supply, and comparable to many high-voltage switched-capacitor (SC) ADC. Implemented in a 0.18mum CMOS process, the ADC obtains a peak SNR of 45dB and SFDR of 52.6dB while dissipating only 30mW

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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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