Low Power SOC Design Using Partial-Trench-Isolation ABC SOI (PTI-ABC SOI) for Sub-100-nm LSTP Technology

Abstract

The bodies of partially depleted SOI devices are selectively biased so that circuits operate at low supply voltages without area overhead. Applying forward body bias to logic gates reduces delay variation by 7-21%. A level shifter (LF) and data retention FF (DRFF) circuits can operate at lower supply voltages below 1.0-V when the body bias of the key transistors is suitably controlled. The technology reduces operating and standby power of SOC with 90-nm LSTP CMOS technology by 40 and 98%, respectively