A 15b-Linear, 20MS/s, 1.5b/Stage Pipelined ADC Digitally Calibrated with Signal-Dependent Dithering

Abstract

A signal-dependent dithering concept is developed to measure the multiplying DAC (MDAC) gain error of a 1.5b/stage pipelined ADC in background. A 15b, 20MS/s prototype ADC exhibits SFDR and THD of 98 and -92dB with 14.5MHz input. The chip fabricated in 0.18mum CMOS occupies 2.3 times 1.7mm2, and consumes 285mW at 1.8V