采用65nm CMOS的500MS/s 5b ADC

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705349

B. Ginsburg, A. Chandrakasan

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引用次数: 19

摘要

采用纯数字65nm CMOS技术制作了用于超宽带接收机的1.2V 6mW 500MS/s 5位ADC。ADC采用6通道时间交错连续逼近寄存器结构。每个通道都有一个分裂电容阵列，以减少开关能量和对数字时序倾斜的灵敏度。采用可变延迟线优化锁存器频闪瞬间，减小前置放大器电流

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A 500MS/s 5b ADC in 65nm CMOS

A 1.2V 6mW 500MS/s 5-bit ADC for use in a UWB receiver has been fabricated in a pure digital 65nm CMOS technology. The ADC uses a 6-channel time-interleaved successive approximation register architecture. Each of the channels has a split capacitor array to reduce switching energy and sensitivity to digital timing skew. A variable delay line is used to optimize the instant of latch strobing to reduce preamplifier currents

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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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