基于CMOS的2.3mW基带脉冲超宽带收发器前端

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705379

Ian D O 'donnell, R. Brodersen, Clk Gen

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引用次数: 43

摘要

一个高度集成的，灵活的，基带脉冲-超宽带收发器前端已经在标准的0.13mum CMOS工艺中实现，功耗为1.8mW (RX)和0.5mW (TX)， 10脉冲/秒，1.1V电源。该收发器针对传感器网络应用，包括1位，1.92 GSample/s a /D转换，50Omega输入匹配0dB-42dB可变增益，控制逻辑，60MHz振荡器和脉冲发射器。演示了脉冲的发射和接收

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A 2.3mW Baseband Impulse-UWB Transceiver Front-End in CMOS

A highly integrated, flexible, baseband impulse-UWB transceiver front-end has been implemented in a standard 0.13mum CMOS process with power consumption of 1.8mW (RX) and 0.5mW (TX) at 10 Mpulses/s with a 1.1V supply. This transceiver targets a sensor network application and comprises a 1-bit, 1.92 GSample/s A/D conversion, 50Omega input matching with 0dB-42dB variable gain, control logic, 60MHz oscillator, and a pulse transmitter. Pulse transmission and reception are demonstrated

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来源期刊

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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