A 35-Gb/s Limiting Amplifier in 0.13/spl mu/m CMOS Technology

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705340

Chihun Lee, Shen-Iuan Liu

引用次数: 7

Abstract

A 35Gb/s limiting amplifier using cascaded-distributed amplifiers with active feedback and on-chip transformers achieves a differential gain SDD21 of 38 dB and a bandwidth of 26.2GHz. It has been fabricated in 0.13mum CMOS technology. It exhibits a single-ended output swing of 300mVPP while consuming 125mW from a 1.5V supply

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基于0.13/spl mu/m CMOS技术的35 gb /s限幅放大器

35Gb/s限制放大器采用带有源反馈和片上变压器的级联分布式放大器，差分增益SDD21为38 dB，带宽为26.2GHz。它是用0.13 μ m CMOS技术制造的。它的单端输出摆幅为300mVPP，同时从1.5V电源消耗125mW

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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