15b线性，20MS/s, 1.5b/级流水线ADC数字校准与信号相关的抖动

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705388

Yun-Shiang Shu, B. Song

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引用次数: 18

摘要

提出了一种信号相关的抖动概念，用于测量1.5b/级流水线ADC在后台的倍增DAC (MDAC)增益误差。一个15b, 20MS/s的原型ADC在14.5MHz输入时的SFDR和THD分别为98和-92dB。该芯片采用0.18 μ m CMOS工艺，占地2.3 × 1.7mm2，功耗285mW，电压为1.8V

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A 15b-Linear, 20MS/s, 1.5b/Stage Pipelined ADC Digitally Calibrated with Signal-Dependent Dithering

A signal-dependent dithering concept is developed to measure the multiplying DAC (MDAC) gain error of a 1.5b/stage pipelined ADC in background. A 15b, 20MS/s prototype ADC exhibits SFDR and THD of 98 and -92dB with 14.5MHz input. The chip fabricated in 0.18mum CMOS occupies 2.3 times 1.7mm2, and consumes 285mW at 1.8V

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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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