A 1-ps Resolution On-Chip Sampling Oscilloscope with 64:1 Tunable Sampling Range Based on Ramp Waveform Division Scheme

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705312

K. Inagaki, D. Antono, M. Takamiya, S. Kumashiro, T. Sakurai

引用次数: 22

Abstract

An on-chip sampling oscilloscope with lps timing resolution is realized in 90nm CMOS process based on a proposed ramp waveform division scheme for precise signal integrity and power-line integrity measurement. The resolution in time is variable from 1ps to 64ps in 64 steps. A novel on-chip inductance measurement procedure is also proposed

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基于斜坡波形分割方案的64:1可调采样范围的1-ps分辨率片上采样示波器

基于所提出的斜坡波形分频方案，在90nm CMOS工艺上实现了具有lp时序分辨率的片上采样示波器，可实现精确的信号完整性和电力线完整性测量。在64步中，时间分辨率从1ps到64ps不等。提出了一种新的片上电感测量方法

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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