带数字背景校准的14-b 150ms /s CMOS DAC

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705307

Hsing-Hung Chen, Jaesik Lee, J. Weiner, Young-Kai Chen, Jiunn-Tsair Chen

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引用次数: 18

摘要

介绍了一种采用背景校准技术的14b型150MS/s电流转向DAC。数字背景校准环路对静态性能的影响小于plusmn 0.55 LSB。在采样率为150MS/s时，该DAC在1.6MHz时可实现81dB的无杂散动态范围(SFDR)，在48.75MHz时可实现67dB的无杂散动态范围。该DAC采用0.35 mm CMOS工艺，有源面积为2.4 × 1.2 mm2

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A 14-b 150 MS/s CMOS DAC with Digital Background Calibration

A 14-b 150MS/s current-steering DAC with background calibration technique is demonstrated. Digital background calibration loop trims the static performance less than plusmn 0.55 LSB. The DAC achieves the spurious free dynamic range (SFDR) of 81dB at 1.6MHz and 67dB at 48.75MHz for sampling rate of 150MS/s. The DAC is implemented in a 0.35 mum CMOS process and active area is a 2.4times1.2 mm2

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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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