A 10-Gb/s CMOS Merged Adaptive Equalizer/CDR Circuit for Serial-Link Receivers

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705376

S. Gondi, B. Razavi

引用次数: 6

Abstract

A merged equalizer/CDR circuit employs a parallel-path equalizer and triple-loop adaptation to achieve a binary data rate of 10 Gb/s. Realized in 0.13mum CMOS technology, the circuit adapts to FR4 trace lengths up to 24 inches with BER<10-13 while consuming 133 mW from a 1.6-V supply

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用于串行链路接收机的10gb /s CMOS合并自适应均衡器/CDR电路

合并均衡器/CDR电路采用并行路径均衡器和三环自适应，实现了10gb /s的二进制数据速率。该电路采用0.13 μ m CMOS技术实现，可适应FR4走线长度达24英寸，BER<10-13，同时从1.6 v电源消耗133 mW

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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