A. Momtaz, D. Chung, N. Kocaman, M. Caresosa, J. Cao, Bo Zhang, I. Fujimori
{"title":"A Fully Integrated 10Gbps Receiver with Adaptive Optical Dispersion Equalizer in 0.13/spl mu/m CMOS","authors":"A. Momtaz, D. Chung, N. Kocaman, M. Caresosa, J. Cao, Bo Zhang, I. Fujimori","doi":"10.1109/VLSIC.2006.1705338","DOIUrl":null,"url":null,"abstract":"A 10Gbps receiver, containing an adaptive equalizer, a clock and data recovery (CDR), and a demultiplexer, is implemented in 0.13 mum CMOS. By compensating for optical dispersion, this chip recovers transmitted data after 200km of single-mode fiber at BER < 10-12 . Use of analog equalizer with digital adaptation garners total power dissipation of 950mW","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2006.1705338","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A 10Gbps receiver, containing an adaptive equalizer, a clock and data recovery (CDR), and a demultiplexer, is implemented in 0.13 mum CMOS. By compensating for optical dispersion, this chip recovers transmitted data after 200km of single-mode fiber at BER < 10-12 . Use of analog equalizer with digital adaptation garners total power dissipation of 950mW