高频时钟的占空比校正电路

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705332

K. Agarwal, R. Montoye

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引用次数: 16

摘要

我们提出了一种控制高频时钟占空比的电路，具有很好的分辨率。所提出的占空比检测和校正电路是数字的，不需要外部参考和匹配器件。该电路设计用于补偿使用有限开关动态逻辑(LSDL)实现的浮点单元中的占空比不确定性(Belloumini, 2005)。结果表明，在25% ~ 75%的输入范围内，该电路对8ghz时钟的占空比校正精度为±0.8%

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A Duty-Cycle Correction Circuit for High-Frequency Clocks

We present a circuit to control duty-cycle of high-frequency clocks with very fine resolution. The proposed duty-cycle detection and correction circuits are digital and do not require external references and matching devices. The circuits are designed to compensate for duty-cycle uncertainties in a floating point unit implemented using limited switch dynamic logic (LSDL) (Belloumini, 2005). The results show that the circuit can correct the duty-cycle of an 8-GHz clock with plusmn0.8% accuracy for an input range of 25% to 75%

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来源期刊

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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