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引用次数: 3
摘要
提出了一种在2.5V 0.25 ma CMOS工艺下，输出速率为5MS/s, DR为85dB的连续δ - σ A/D调制器。该调制器具有单级双环结构，允许近一个时钟周期的多余环路延迟。采用多位量化器提高分辨率，采用非归零dac降低时钟抖动灵敏度。利用电容调谐来克服工艺变化。校准是为了抑制DAC失配。时钟在60MHz，芯片消耗50mw
A 14-Bit 5MS/s Continuous-Time Delta-Sigma A/D Modulator
A continuous-time delta-sigma A/D modulator providing 85dB DR with 5MS/s output rate in a 2.5V 0.25mum CMOS process is presented. The modulator has a single-stage, dual-loop architecture allowing nearly one clock period excess loop delay. A multi-bit quantizer is used to increase resolution and non-return-to-zero DACs are adopted to reduce clock jitter sensitivity. Capacitor tuning is utilized to overcome process variation. Calibration is implemented to suppress DAC mismatch. Clocked at 60MHz, the chip consumes 50 mW
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