{"title":"A 0.5-V 1-Msample/s 60-dB SNDR Track-and-Hold Circuit","authors":"S. Chatterjee, P. Kinget","doi":"10.1109/VLSIC.2006.1705304","DOIUrl":null,"url":null,"abstract":"A 0.5V 1Msps track-and-hold (T/H) circuit with a 60dB SNDR is presented. The fully-differential circuit is implemented in a 0.25mum CMOS technology, with standard 0.6V VT devices, and uses true low voltage design techniques i.e. with no clock and no voltage boosting","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2006.1705304","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A 0.5V 1Msps track-and-hold (T/H) circuit with a 60dB SNDR is presented. The fully-differential circuit is implemented in a 0.25mum CMOS technology, with standard 0.6V VT devices, and uses true low voltage design techniques i.e. with no clock and no voltage boosting