A 14-Bit 5MS/s Continuous-Time Delta-Sigma A/D Modulator

Abstract

A continuous-time delta-sigma A/D modulator providing 85dB DR with 5MS/s output rate in a 2.5V 0.25mum CMOS process is presented. The modulator has a single-stage, dual-loop architecture allowing nearly one clock period excess loop delay. A multi-bit quantizer is used to increase resolution and non-return-to-zero DACs are adopted to reduce clock jitter sensitivity. Capacitor tuning is utilized to overcome process variation. Calibration is implemented to suppress DAC mismatch. Clocked at 60MHz, the chip consumes 50 mW