{"title":"基于0.13/spl mu/ m CMOS技术的1.2V 37-38.5GHz 8相时钟发生器","authors":"Chihun Lee, Lan-Cho Chou, Shen-Iuan Liu, Chun-Lin Ko, Y. Juang, Chin-Fong Chiu","doi":"10.1109/VLSIC.2006.1705295","DOIUrl":null,"url":null,"abstract":"A 37-38.5GHz octave-phase clock generator is presented. An octave-phase LC voltage-controlled oscillator and the split-load divider are presented. The proposed PD improves the static phase error and enhances the gain. The clock generator has been fabricated in 0.13mum CMOS technology. It achieves the rms jitter of 0.24ps at 38GHz while consuming 51.6mW without buffers from a 1.2V supply","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"96 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A 1.2V 37-38.5GHz 8-Phase Clock Generator in 0.13/spl mu/ m CMOS Technology\",\"authors\":\"Chihun Lee, Lan-Cho Chou, Shen-Iuan Liu, Chun-Lin Ko, Y. Juang, Chin-Fong Chiu\",\"doi\":\"10.1109/VLSIC.2006.1705295\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 37-38.5GHz octave-phase clock generator is presented. An octave-phase LC voltage-controlled oscillator and the split-load divider are presented. The proposed PD improves the static phase error and enhances the gain. The clock generator has been fabricated in 0.13mum CMOS technology. It achieves the rms jitter of 0.24ps at 38GHz while consuming 51.6mW without buffers from a 1.2V supply\",\"PeriodicalId\":366835,\"journal\":{\"name\":\"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.\",\"volume\":\"96 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2006.1705295\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2006.1705295","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
摘要
提出了一种37 ~ 38.5 ghz倍频相时钟发生器。介绍了一种八度相LC压控振荡器和分载分压器。该方法改善了静态相位误差，提高了增益。时钟发生器采用0.13 μ m CMOS工艺制造。它在38GHz时实现0.24ps的有效值抖动，同时从1.2V电源消耗51.6mW而不含缓冲
A 1.2V 37-38.5GHz 8-Phase Clock Generator in 0.13/spl mu/ m CMOS Technology
A 37-38.5GHz octave-phase clock generator is presented. An octave-phase LC voltage-controlled oscillator and the split-load divider are presented. The proposed PD improves the static phase error and enhances the gain. The clock generator has been fabricated in 0.13mum CMOS technology. It achieves the rms jitter of 0.24ps at 38GHz while consuming 51.6mW without buffers from a 1.2V supply
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