A 12b, 75MS/s Pipelined ADC Using Incomplete Settling

Abstract

This paper proposes a mixed-signal technique that exploits incomplete settling to achieve ultra low power residue amplification. In the first stage of the presented 12-bit, 75-MS/s prototype ADC, the employed open-loop gain stage dissipates only 2.9mW from a 3V supply, achieving a 94% power reduction over a typical op-amp implementation. The complete pipelined ADC achieves a measured SNR of 66dB (fin = 1MHz), consumes 273mW and occupies 7.9mm in 0.35mum CMOS