1.047GHz, 1.2V, 90nm CMOS, 2-Way VLIW DSP Core Using Saturation Anticipator Circuit

H. Suzuki, H. Takata, H. Shinohara, E. Teraoka, M. Matsuo, T. Yoshida, H. Sato, N. Honda, N. Masui, T. Shimizu
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引用次数: 1

Abstract

1.047GHz synthesizable 2-way VLIW general purpose DSP core has been developed by 1.2V 90nm CMOS technology. The key technology is to detect saturation from adder's inputs in an ALU and parallelize the saturation check with the adder operation. The proposed saturation anticipator circuit and the logic structure optimization improve DSP's clock frequency by 20.8%. The test chip also runs 0. 10muW/MHz at 0.8V low power operation mode
1.047GHz, 1.2V, 90nm CMOS,采用饱和预估电路的2路VLIW DSP核心
采用1.2V 90nm CMOS技术开发了1.047GHz可合成双向VLIW通用DSP核心。关键技术是检测ALU中加法器输入的饱和度,并将饱和度检查与加法器操作并行化。提出的饱和预估电路和逻辑结构优化使DSP时钟频率提高了20.8%。测试芯片也运行0。10muW/MHz, 0.8V低功耗工作模式
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