{"title":"一个12位32 /spl mu/W比例无关算法ADC","authors":"J. Jarvinen, M. Saukoski, K. Halonen","doi":"10.1109/VLSIC.2006.1705305","DOIUrl":null,"url":null,"abstract":"This paper describes a ratio-independent algorithmic ADC architecture that requires a single differential amplifier and a comparator. The prototype 12-bit, 41.67 kS/s ADC with an active die area of 0.055 mm2 is implemented in a 0.13mum CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 32 muW power dissipation, the ADC achieves 80 dB SFDR and 60 dB SNDR, resulting in a power FOM of 0.9 pJ/conversion","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A 12-Bit 32 /spl mu/W Ratio-Independent Algorithmic ADC\",\"authors\":\"J. Jarvinen, M. Saukoski, K. Halonen\",\"doi\":\"10.1109/VLSIC.2006.1705305\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a ratio-independent algorithmic ADC architecture that requires a single differential amplifier and a comparator. The prototype 12-bit, 41.67 kS/s ADC with an active die area of 0.055 mm2 is implemented in a 0.13mum CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 32 muW power dissipation, the ADC achieves 80 dB SFDR and 60 dB SNDR, resulting in a power FOM of 0.9 pJ/conversion\",\"PeriodicalId\":366835,\"journal\":{\"name\":\"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2006.1705305\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2006.1705305","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
摘要
本文描述了一种比例无关的算法ADC结构，它只需要一个差分放大器和一个比较器。原型12位，41.67 kS/s，有效芯片面积为0.055 mm2，在0.13 mm CMOS中实现。采用动态偏置运算放大器使功耗最小化。该ADC功耗为32 muW，可实现80 dB的SFDR和60 dB的SNDR，功率FOM为0.9 pJ/转换
A 12-Bit 32 /spl mu/W Ratio-Independent Algorithmic ADC
This paper describes a ratio-independent algorithmic ADC architecture that requires a single differential amplifier and a comparator. The prototype 12-bit, 41.67 kS/s ADC with an active die area of 0.055 mm2 is implemented in a 0.13mum CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 32 muW power dissipation, the ADC achieves 80 dB SFDR and 60 dB SNDR, resulting in a power FOM of 0.9 pJ/conversion
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
