A Tunable Passive Filter for Low-Power High-Speed Equalizers

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705378

Ruifeng Sun, Jaejin Park, F. O’Mahony, C. Yue

引用次数: 20

Abstract

This paper presents the design and implementation of an integrated tunable passive filter for low-power continuous-time adaptive equalization. Based on a broadband matched high-pass filter topology, a PMOS biased in linear region is used to adjust the low-frequency attenuation for equalizing channel losses. A 0.13-mum prototype demonstrates gain compensation up to 17 dB at 5 GHz without any power consumption

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用于低功率高速均衡器的可调谐无源滤波器

本文介绍了一种集成可调谐无源滤波器的设计与实现，用于低功率连续时间自适应均衡。基于宽带匹配高通滤波器拓扑，采用线性偏置的PMOS调节低频衰减，均衡信道损耗。一个0.13 μ m的原型演示了增益补偿高达17 dB，在5 GHz下没有任何功耗

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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