A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses

T. Suzuki, H. Yamauchi, Y. Yamagami, K. Satomi, H. Akamatsu
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引用次数: 25

Abstract

A guarantee obligation of keeping the cell-margin against a simultaneously read and write (R/W) disturbed accesses in the same column is required to a 2-port SRAM. We verified that it is difficult to provide these margins without any decrease in cell-current and any increase in cell-area penalty only by using the previously proposed techniques so far. To solve this, we have developed the new cell design technology for an 8-Tr 2-port cell in a 65-nm CMOS technology and have demonstrated that the R/W margins can be improved by 45%/70%, respectively at 0.9V, and the cell-size can be reduced by 20% compared with the conventional column-based Vdd control. Another 7-Tr cell which can reduce cell-area by 31% has been also demonstrated
一种稳定的SRAM单元设计,可同时抵抗读写干扰
2端口SRAM需要保证在同一列中同时读写(R/W)干扰访问时保持cell-margin的保证义务。我们证实,仅通过使用先前提出的技术,很难在不减少细胞电流和增加细胞面积惩罚的情况下提供这些边际。为了解决这个问题,我们开发了一种新的电池设计技术,用于65纳米CMOS技术的8-Tr 2端口电池,并证明了在0.9V时R/W边际分别可以提高45%/70%,与传统的基于柱的Vdd控制相比,电池尺寸可以减少20%。另一种可将细胞面积减少31%的7-Tr细胞也已被证实
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