{"title":"用于低功率高速均衡器的可调谐无源滤波器","authors":"Ruifeng Sun, Jaejin Park, F. O’Mahony, C. Yue","doi":"10.1109/VLSIC.2006.1705378","DOIUrl":null,"url":null,"abstract":"This paper presents the design and implementation of an integrated tunable passive filter for low-power continuous-time adaptive equalization. Based on a broadband matched high-pass filter topology, a PMOS biased in linear region is used to adjust the low-frequency attenuation for equalizing channel losses. A 0.13-mum prototype demonstrates gain compensation up to 17 dB at 5 GHz without any power consumption","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"180 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"A Tunable Passive Filter for Low-Power High-Speed Equalizers\",\"authors\":\"Ruifeng Sun, Jaejin Park, F. O’Mahony, C. Yue\",\"doi\":\"10.1109/VLSIC.2006.1705378\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design and implementation of an integrated tunable passive filter for low-power continuous-time adaptive equalization. Based on a broadband matched high-pass filter topology, a PMOS biased in linear region is used to adjust the low-frequency attenuation for equalizing channel losses. A 0.13-mum prototype demonstrates gain compensation up to 17 dB at 5 GHz without any power consumption\",\"PeriodicalId\":366835,\"journal\":{\"name\":\"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.\",\"volume\":\"180 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2006.1705378\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2006.1705378","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Tunable Passive Filter for Low-Power High-Speed Equalizers
This paper presents the design and implementation of an integrated tunable passive filter for low-power continuous-time adaptive equalization. Based on a broadband matched high-pass filter topology, a PMOS biased in linear region is used to adjust the low-frequency attenuation for equalizing channel losses. A 0.13-mum prototype demonstrates gain compensation up to 17 dB at 5 GHz without any power consumption