功率/性能/通道长度的权衡1.6至9.6Gbps的I/O链路在90nm CMOS服务器，桌面和移动应用程序

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705321

E. Yeung, K. Canagasaby, A. Tripathi, S. Chaudhuri, P. Meier, J. Prijić, V. Joshi, M. Mazumder, S. Dabral

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引用次数: 5

摘要

在1.2V 90nm CMOS测试芯片上，对1.6 ~ 9.6Gbps服务器、桌面和移动I/O链路的性能和功耗进行了比较，该芯片实现了均衡电压模式和电流模式驱动、TX和RX均衡器、自偏置环形振荡器和LC锁相环以及不同的RX时钟方案。电压模式驱动(均衡或不均衡)和RX均衡器的新颖组合提供了最低的功率(在7.2Gbps时为12.1mW/Gbps)，为短距离链路提供了低功耗选择

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Power/Performance/Channel Length Tradeoffs in 1.6 to 9.6Gbps I/O Links in 90nm CMOS for Server, Desktop, and Mobile Applications

Performance and power of 1.6 to 9.6Gbps server, desktop, and mobile I/O links in a 1.2V 90nm CMOS test chip implementing equalized voltage-mode and current-mode drivers, TX and RX equalizers, self-biased ring oscillator and LC PLLs, and different RX clocking schemes are compared. The novel combination of voltage-mode driver (equalized or unequalized) and RX equalizer delivers the lowest power (12.1mW/Gbps at 7.2Gbps), offering a low-power option for short-distance links

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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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