用于下一代WLAN的11位330MHz 8X OSR /spl Sigma/-spl Delta/调制器

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705362

J. Paramesh, R. Bishop, K. Soumyanath, David Allstot

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引用次数: 10

摘要

带4位内部量化器的2-2级联Sigma-Delta调制器以40MSPS的转换速率将WLAN信号数字化。采用标称vt器件和金属梳状电容器在90nm CMOS上实现，占地1.3mm2的核心面积，在330MHz下实现67dB信噪比、63dB峰值SNDR和67dB峰值SFDR, 1.4V电源功耗78mW

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An 11-Bit 330MHz 8X OSR /spl Sigma/-spl Delta/ Modulator for Next-Generation WLAN

A 2-2 cascaded Sigma-Delta modulator with 4-bit internal quantizers digitizes WLAN signals with 40MSPS conversion rate. Implemented in 90nm CMOS using nominal-Vt devices and metal comb capacitors, it occupies 1.3mm2 core area, achieves 67dB SNR, 63dB peak SNDR and 67dB peak SFDR at 330MHz, and dissipates 78mW from a 1.4V supply

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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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