J. Paramesh, R. Bishop, K. Soumyanath, David Allstot
{"title":"An 11-Bit 330MHz 8X OSR /spl Sigma/-spl Delta/ Modulator for Next-Generation WLAN","authors":"J. Paramesh, R. Bishop, K. Soumyanath, David Allstot","doi":"10.1109/VLSIC.2006.1705362","DOIUrl":null,"url":null,"abstract":"A 2-2 cascaded Sigma-Delta modulator with 4-bit internal quantizers digitizes WLAN signals with 40MSPS conversion rate. Implemented in 90nm CMOS using nominal-Vt devices and metal comb capacitors, it occupies 1.3mm2 core area, achieves 67dB SNR, 63dB peak SNDR and 67dB peak SFDR at 330MHz, and dissipates 78mW from a 1.4V supply","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2006.1705362","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
A 2-2 cascaded Sigma-Delta modulator with 4-bit internal quantizers digitizes WLAN signals with 40MSPS conversion rate. Implemented in 90nm CMOS using nominal-Vt devices and metal comb capacitors, it occupies 1.3mm2 core area, achieves 67dB SNR, 63dB peak SNDR and 67dB peak SFDR at 330MHz, and dissipates 78mW from a 1.4V supply