发布求助
文献互助 智能选刊 最新文献

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)最新文献

筛选
英文 中文
Novel 3-dimensional 46F/sup 2/ SRAM technology with 0.294um/sup 2/ S/sup 3/ (stacked single-crystal Si) cell and SSTFT (stacked single-crystal thin film transistor) 新颖的三维46F/sup 2/ SRAM技术，采用0.294um/sup 2/ S/sup 3/(堆叠单晶Si)电池和SSTFT(堆叠单晶薄膜晶体管)
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356587
J.H. Jang, S. Jung, Y.H. Kang, W.S. Cho, J.H. Moon, C. Yeo, K. Kwak, B.H. Choi, B. Hwang, W. Jung, S. Kim, J. Kim, J. Na, H. Lim, J. Jeong, Kinam Kim
{"title":"Novel 3-dimensional 46F/sup 2/ SRAM technology with 0.294um/sup 2/ S/sup 3/ (stacked single-crystal Si) cell and SSTFT (stacked single-crystal thin film transistor)","authors":"J.H. Jang, S. Jung, Y.H. Kang, W.S. Cho, J.H. Moon, C. Yeo, K. Kwak, B.H. Choi, B. Hwang, W. Jung, S. Kim, J. Kim, J. Na, H. Lim, J. Jeong, Kinam Kim","doi":"10.1109/ESSDER.2004.1356587","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356587","url":null,"abstract":"We have realized a 46F/sup 2/ SRAM cell size of 0.294 /spl mu/m/sup 2/ with 80 nm technology and single stack S/sup 3/ cell technology. SSTFTs and vertical node contacts are major keys in the S/sup 3/ cell technology. The stacked single crystal silicon thin film is developed for the load pMOS SSTFT of the S/sup 3/ SRAM cell. The load pMOS SSTFT is stacked on ILD to reduce the SRAM cell size. Fully working 64 Mbit SRAM is achieved by this S/sup 3/ cell technology. The basic reliability of SSTFT, with 80 nm length, is also investigated in this study.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133456746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of strained-silicon-on-insulator double-gate MOS structures 应变绝缘子上硅双栅MOS结构分析
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356516
N. Barin, C. Fiegna, E. Sangiorgi
{"title":"Analysis of strained-silicon-on-insulator double-gate MOS structures","authors":"N. Barin, C. Fiegna, E. Sangiorgi","doi":"10.1109/ESSDER.2004.1356516","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356516","url":null,"abstract":"Ultra-thin body double-gate (DG) MOS structures with strained silicon are investigated by the solution of the 1D Schrodinger and Poisson equations, with open boundary conditions on the wave functions in the gate electrodes. The electrostatics of this device architecture and its dependence on the amount of strain and on the thickness of the silicon layer is analyzed in terms of subband structure, subband population, carrier distribution within the strained-silicon layer, charge-voltage characteristics and gate tunneling current.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"312 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133748985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Interface passivation mechanisms in metal gated oxide capacitors 金属门控氧化物电容器的界面钝化机制
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356555
G. Lujan, T. Schram, G. Sjoblom, T. Witters, S. Kubicek, S. De Gendt, M. Heyns, K. De Meyer
{"title":"Interface passivation mechanisms in metal gated oxide capacitors","authors":"G. Lujan, T. Schram, G. Sjoblom, T. Witters, S. Kubicek, S. De Gendt, M. Heyns, K. De Meyer","doi":"10.1109/ESSDER.2004.1356555","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356555","url":null,"abstract":"We use the conductance technique to measure the density of interface states, D/sub it/, in MOS capacitors with metal gate electrodes. D/sub it/ as a function of the band gap is extracted for a series of capacitors. ALD TiN electrodes show poor passivation while PVD TaN electrodes do not. There is no evidence that the poor passivation in the TiN electrodes is because of low hydrogen diffusion through the metal oxide stack. Possibly, the strain induced by the ALD metal layer or contamination from the metal precursors are responsible for the poor passivation.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114118049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
90nm RF CMOS technology for low-power 900MHz applications [amplifier example] 用于低功耗900MHz应用的90nm RF CMOS技术[放大器示例]
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356556
J. Ramos, A. Mercha, W. Jeamsaksiri, D. Linten, S. Jenei, R. Rooyackers, R. Verbeeck, S. Thijs, A. Scholten, P. Wambacq, I. Debusschere, S. Decoutere
{"title":"90nm RF CMOS technology for low-power 900MHz applications [amplifier example]","authors":"J. Ramos, A. Mercha, W. Jeamsaksiri, D. Linten, S. Jenei, R. Rooyackers, R. Verbeeck, S. Thijs, A. Scholten, P. Wambacq, I. Debusschere, S. Decoutere","doi":"10.1109/ESSDER.2004.1356556","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356556","url":null,"abstract":"This work emphasizes the low power capabilities of a 90 nm RF CMOS technology and a portfolio of high Q passive components for low-power portable applications around 900 MHz. The experimental results mainly focus on the trade-off needed to account for an optimal operation in weak inversion for low-power applications. The DC gain, the bandwidth and the distortion are discussed to evaluate the possibilities offered by the CMOS technology scaling. The achievements are illustrated for the first time by the good performance of a fully integrated low-noise amplifier operating in moderate inversion at 900 MHz.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125798838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Optimized cell structure for FinFET array Flash memory 优化了FinFET阵列闪存的单元结构
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356546
E. Cho, T.Y. Kim, C.H. Lee, C. Lee, J. Yoon, H. Cho, H. Kang, Y. Ahn, Donggun Park, Kinam Kim
{"title":"Optimized cell structure for FinFET array Flash memory","authors":"E. Cho, T.Y. Kim, C.H. Lee, C. Lee, J. Yoon, H. Cho, H. Kang, Y. Ahn, Donggun Park, Kinam Kim","doi":"10.1109/ESSDER.2004.1356546","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356546","url":null,"abstract":"In this paper, a highly manufacturable 256 M body tied tri-gate fin array NOR-type Flash memory, with 70 nm fin width, was successfully fabricated and the characteristics were compared with planar cell array transistors. In this experiment, a 1.6 times higher driving current of the fin array flash memory cell transistor is achieved than that of a planar device with the same gate length. We propose an optimized fin structure for flash memory operation and a direction for enhanced current of the fin array flash memory cell transistor with respect to the channel silicon plane, coupling ratio, junction profile and anti-punch through implantation conditions.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125450354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Phase-change memory technology for embedded applications 嵌入式应用的相变存储器技术
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356547
F. Ottogalli, A. Pirovano, F. Pellizzer, M. Tosi, P. Zuliani, P. Bonetalli, R. Bez
{"title":"Phase-change memory technology for embedded applications","authors":"F. Ottogalli, A. Pirovano, F. Pellizzer, M. Tosi, P. Zuliani, P. Bonetalli, R. Bez","doi":"10.1109/ESSDER.2004.1356547","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356547","url":null,"abstract":"A novel p-trench phase-change memory (PCM) cell and its integration with a MOSFET selector in a standard 0.18 /spl mu/m CMOS technology are presented. The high-performance capabilities of PCM cells are experimentally investigated and their application in embedded systems is discussed. Write times as low as 10 ns and 20 ns have been measured for the RESET and SET operation, respectively, still granting a 10/spl times/ read margin. The impact of the RESET pulse on PCH cell endurance has been also evaluated. Finally, cell distributions and first statistical endurance measurements on a 4 Mbit MOS demonstrator clearly assess the feasibility of the PCM technology.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130219448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
FinFET SRAM for high-performance low-power applications 用于高性能低功耗应用的FinFET SRAM
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356490
R. Joshi, R.Q. Williams, E. Nowak, K. Kim, J. Beintner, T. Ludwig, I. Aller, C. Chuang
{"title":"FinFET SRAM for high-performance low-power applications","authors":"R. Joshi, R.Q. Williams, E. Nowak, K. Kim, J. Beintner, T. Ludwig, I. Aller, C. Chuang","doi":"10.1109/ESSDER.2004.1356490","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356490","url":null,"abstract":"The SRAM behavior of FinFET technology is investigated and compared with 90 nm node planar partially-depleted silicon-on-insulator (PD-SOI) technology. Unique FinFET circuit behavior in SRAM applications, resulting from the near-ideal device characteristics, is demonstrated by full cell cross section simulation for the first time, and shows high performance and low active and standby power. SRAM stability is analyzed in detail, as compared to PD-SOI.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126201912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
Study of electrically active defects in high mobility HfO/sub 2/ MOSFETs 高迁移率HfO/ sub2 / mosfet中电活性缺陷的研究
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356519
L. Militaru, O. Weber, M. Muller, F. Ducroquet, D. Dusciac, C. Plossu, T. Ernst, B. Guillaumot, S. Deleonibus, T. Skotnicki
{"title":"Study of electrically active defects in high mobility HfO/sub 2/ MOSFETs","authors":"L. Militaru, O. Weber, M. Muller, F. Ducroquet, D. Dusciac, C. Plossu, T. Ernst, B. Guillaumot, S. Deleonibus, T. Skotnicki","doi":"10.1109/ESSDER.2004.1356519","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356519","url":null,"abstract":"We present a detailed analysis of electrically active gate oxide defects on damascene CMOS devices with a HfO/sub 2/ gate dielectric and a TiN/W gate electrode. The interface state density (D/sub it/) and the trapped oxide charge (N/sub it/) are determined by 2 and 3-level charge pumping analysis on high-quality nMOS and pMOS transistors. Furthermore, we discuss the influence of the gate stack defects on the carrier mobility in the channel and correlate the reduction of the gate oxide defect density to a mobility improvement for both electrons and holes.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124515083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Novel gate concepts for MOS devices MOS器件的新型栅极概念
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356484
J. Colinge
{"title":"Novel gate concepts for MOS devices","authors":"J. Colinge","doi":"10.1109/ESSDER.2004.1356484","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356484","url":null,"abstract":"The classical MOSFET has a single gate electrode located at the top of the device. Recently, multiple-gate devices have been made using SOI substrates. The multiple-gate structure offers the benefit of potentially higher current drive and reduce short-channel effects. This paper compares the advantages of double-gate structures such as the FinFET, triple-gate structures, and \"triple-plus\"-gate devices such as the pi-gate and omega-gate MOSFETs.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"274 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115998129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Technology considerations for automotive 汽车的技术考虑
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356480
H. Casier, P. Moens, K. Appeltans
{"title":"Technology considerations for automotive","authors":"H. Casier, P. Moens, K. Appeltans","doi":"10.1109/ESSDER.2004.1356480","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356480","url":null,"abstract":"In this paper, the evolution of automotive electronics and the specific electronics requirements posed by the automotive environment are discussed. Safety is a very dominant factor in automotive applications and this has a large impact on the required robustness of the electronics. As an example, DMOS optimization and ESD robustness considerations have led to the N-epi based structure of the AMIS I3T automotive technology. On top of the robust technology, innovative design techniques are described which further improve the robustness of the high voltage smart power applications for the harsh environment of the automotive electronics.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128723849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信