Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)最新文献

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Investigation of InP/InGaAs pnp /spl delta/-doped heterojunction bipolar transistor InP/InGaAs pnp /spl δ /掺杂异质结双极晶体管的研究
J. Tsai, King-Poul Zhu, Ying-Cheng Chu, S. Chiu
{"title":"Investigation of InP/InGaAs pnp /spl delta/-doped heterojunction bipolar transistor","authors":"J. Tsai, King-Poul Zhu, Ying-Cheng Chu, S. Chiu","doi":"10.1109/ESSDER.2004.1356584","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356584","url":null,"abstract":"An InP/InGaAs /spl delta/-doped pnp heterojunction bipolar transistor (HBT) has been successfully fabricated and demonstrated for the first time. The addition of a /spl delta/-doped sheet between two undoped spacer layers more effectively eliminates the potential spike at the emitter-base junction, lowers the emitter-collector offset voltage, and increases the effective barrier for electrons, simultaneously. A maximum current gain of 50 and a low offset voltage of 70 mV are obtained, respectively. To our knowledge, the offset voltage of the studied device is the best reported for InP/InGaAs pnp HBTs.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122308799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low voltage and low power aspects of data converter design 低电压和低功耗方面的数据转换器设计
Qiuting Huang
{"title":"Low voltage and low power aspects of data converter design","authors":"Qiuting Huang","doi":"10.1109/ESSDER.2004.1356478","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356478","url":null,"abstract":"Low voltage design is becoming an important issue for analogue circuits expected to operate around 1 V supply in sub 100 nm CMOS technologies. This contribution discusses the impact of low voltage on circuit architecture, opamp configuration to maintain speed and DC gain, common-mode feedback and its stability, switching speed, as well as trends in achievable signal to noise ratio and speed for a given power consumption.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122510493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
The 1/f noise versus sheet resistance in poly-Si is similar to poly-SiGe resistors and Au-layers 多晶硅中的1/f噪声与薄片电阻类似于多晶硅电阻和au层
L. Vandamme, H. Casier
{"title":"The 1/f noise versus sheet resistance in poly-Si is similar to poly-SiGe resistors and Au-layers","authors":"L. Vandamme, H. Casier","doi":"10.1109/ESSDER.2004.1356565","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356565","url":null,"abstract":"We investigated the dependence of 1/f noise on sheet resistance in poly crystalline resistors. The analysis is based on Hooge's empirical relation. The 1/f noise is given by S/sub R//R/sup 2/=C/sub us//WLf. Experimental results on poly-Si are compared with results on poly-SiGe, Ti-silicided poly-Si, metal Au-layers and RuO/sub 2/ based thick film resistors. This review shows that the results are similar and are well described by the relation: C/sub us/=KR/sub sh/ with K=/spl alpha/q/spl mu/ (lowest value 5/spl times/10/sup -13/ /spl mu/m/sup 2///spl Omega/). We explain the difference in 1/f noise between P and B doped samples and deviations from the linear dependence between C/sub us/ and sheet resistance R/sub sh/.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128732230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Impact of STI-induced stress, inverse narrow width effect, and statistical V/sub TH/ variations on leakage currents in 120 nm CMOS sti诱导应力、逆窄宽度效应和统计V/sub TH/变化对120nm CMOS漏电流的影响
C. Pacha, B. Martin, K. von Arnim, R. Brederlow, D. Schmitt-Landsiedel, P. Seegebrecht, J. Berthold, R. Thewes
{"title":"Impact of STI-induced stress, inverse narrow width effect, and statistical V/sub TH/ variations on leakage currents in 120 nm CMOS","authors":"C. Pacha, B. Martin, K. von Arnim, R. Brederlow, D. Schmitt-Landsiedel, P. Seegebrecht, J. Berthold, R. Thewes","doi":"10.1109/ESSDER.2004.1356573","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356573","url":null,"abstract":"Leakage currents in 120 nm CMOS technology are dependent on STI-induced stress (STIS), inverse narrow-width effect (INWE), and statistical threshold voltage variations. In this paper, we analyze the impact of these effects on the gate-width dependence of the device off-current density. A threshold voltage model is proposed to describe the observed off-current minimum. STIS dominates the device behavior for large gate widths while INWE determines the off-current for gate widths below 1 /spl mu/m. Statistical threshold voltage variations are relevant for minimum-sized devices.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129801151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
Low power digital circuit design 低功耗数字电路设计
T. Sakurai
{"title":"Low power digital circuit design","authors":"T. Sakurai","doi":"10.1109/ESSDER.2004.1356476","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356476","url":null,"abstract":"The paper describes approaches for achieving low power digital circuits. The approaches are classified from the standpoint of spatial granularity, temporal granularity and variable granularity. The trend is moving from coarse-grain to the finer grain to save more power with the higher engineering cost. The newer approach includes dynamic adaptive control of V/sub DD/ and V/sub TH/ at a block level. The paper also touches on low-power applications.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130602881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Investigation about the high-temperature impact-ionization coefficient in silicon 硅中高温冲击电离系数的研究
S. Reggiani, M. Rudan, E. Gnani, G. Baccarani
{"title":"Investigation about the high-temperature impact-ionization coefficient in silicon","authors":"S. Reggiani, M. Rudan, E. Gnani, G. Baccarani","doi":"10.1109/ESSDER.2004.1356535","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356535","url":null,"abstract":"In this work, we address the problem of field- and temperature-dependence of the impact-ionization coefficient in silicon. A careful prediction of the impact-ionization phenomenon is essential for the design of devices working in high-current/voltage conditions, where self heating is relevant. A new model is proposed, fitted on first-principle calculations, that demonstrates the essential role played by the non-equilibrium Auger effect, which is neglected in standard approaches. The model is corroborated by a theoretical analysis, that confirms the numerical findings about the field and temperature dependencies.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132537759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A novel method for forming gate spacer and its effects on the W/WN/sub x//poly-Si gate stack 一种新的栅极间隔层形成方法及其对W/WN/sub / x/多晶硅栅极叠加的影响
Yong Soo Kim, K. Lim, Jae-Geun Oh, S. Jang, Heung-Jae Cho, Jun-Mo Yang, J. Suh, Su-Ock Chung, Soo-Young Park, Hong-Seon Yang, H. Sohn, Jin-Woong Kim
{"title":"A novel method for forming gate spacer and its effects on the W/WN/sub x//poly-Si gate stack","authors":"Yong Soo Kim, K. Lim, Jae-Geun Oh, S. Jang, Heung-Jae Cho, Jun-Mo Yang, J. Suh, Su-Ock Chung, Soo-Young Park, Hong-Seon Yang, H. Sohn, Jin-Woong Kim","doi":"10.1109/ESSDER.2004.1356497","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356497","url":null,"abstract":"A novel method for forming the SiO/sub 2//Si/sub 3/N/sub 4/ (O/N) gate spacer has been developed through applying a low temperature atomic layer deposition (ALD) SiO/sub 2/ film. Using this scheme, the Si-O rich interfacial dielectric layer formation and the metal (W) contamination caused by the selective oxidation (SO) process were controlled. Our technique also suppresses the thickness increase of the gate oxide during the SO and enhances the rounding of gate bird's beak (GBB) at the gate edges. Furthermore, the O/N gate spacered device exhibits less junction leakage currents, about 1 order of magnitude lower gate induced drain leakage (GIDL) currents at the same V/sub t/, and better hot carrier degradation (HCD) immunity compared to the N/O/N gated spacer device.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"84 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114336022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of the back gate effect on the breakdown behaviour of SOI LDMOS transistors 后门效应对SOI LDMOS晶体管击穿行为的影响分析
S. Schwantes, T. Florian, M. Graf, F. Dietz, V. Dudek
{"title":"Analysis of the back gate effect on the breakdown behaviour of SOI LDMOS transistors","authors":"S. Schwantes, T. Florian, M. Graf, F. Dietz, V. Dudek","doi":"10.1109/ESSDER.2004.1356537","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356537","url":null,"abstract":"This work investigates the impact of the back gate bias on the drain breakdown behaviour of lateral high voltage SOI transistors with thick epitaxial layers. For the first time, a detailed discussion is presented giving more insight into the physical mechanisms taking place in smart power SOI devices. The results show that five different breakdown mechanisms must be considered. An analytical model that takes the back gate bias and the device parameters into account is presented and verified with a 0.8 /spl mu/m 80 V SOI smart power technology.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"125 1-3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123573228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Universal integrated PIN photodetector 通用集成PIN光电探测器
K. Oberhauser, A. Nemecek, C. Sunder, H. Zimmermann
{"title":"Universal integrated PIN photodetector","authors":"K. Oberhauser, A. Nemecek, C. Sunder, H. Zimmermann","doi":"10.1109/ESSDER.2004.1356561","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356561","url":null,"abstract":"The universal PIN photodetector being realisable in CMOS and BiCMOS technology consists of a common cathode and finger anodes embedded in an intrinsic environment, for fast photogenerated-charge-carrier drift. This finger-anode structure, with rise times below 1 ns, and high responsivity in a wavelength range from 400 nm to 850 nm, permits applications: (i) as a two-anode correlation sensor for optical distance measurements and integrated 3D cameras; and (ii) as a photodiode for optical storage systems CD-ROMs as well as red and blue laser DVDs.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121938017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
On ambient intelligence, needful things and process technologies 关于环境智能、必需品和过程技术
C. van der Poel, F. Pessolano, R. Roovers, F. Widdershoven, G. van de Walle, E. Aarts, P. Christie
{"title":"On ambient intelligence, needful things and process technologies","authors":"C. van der Poel, F. Pessolano, R. Roovers, F. Widdershoven, G. van de Walle, E. Aarts, P. Christie","doi":"10.1109/ESSDER.2004.1356475","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356475","url":null,"abstract":"The ongoing miniaturization of electronic circuits and the corresponding exponential increase in embedded computational power is reaching the point where it becomes viable to integrate electronics into people environments. Ambient intelligence refers to an electronic environment that is sensitive and responsive to the presence of people. Such an environment should be (1) ubiquitous: surrounding the user by a multitude of interconnected systems; (2) transparent: integrated and hidden into the background; (3) intelligent: adapting to the people that live in it. The potential to distribute functionality over a network of devices is determined by the power resources of the device and upon considering these demands it appears helpful to further classify in-home ambient intelligence \"devices\" into three distinct classes: the \"watt-node\", \"milli-watt-node\", and \"micro-watt-node\". In this paper we try to map the system needs associated with these nodes, differing by orders of magnitude with respect to the amount of information to be processed as well as the available power, on to requirements for Si process technology choices.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124741443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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