InP/InGaAs pnp /spl δ /掺杂异质结双极晶体管的研究

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI:10.1109/ESSDER.2004.1356584

J. Tsai, King-Poul Zhu, Ying-Cheng Chu, S. Chiu

{"title":"InP/InGaAs pnp /spl δ /掺杂异质结双极晶体管的研究","authors":"J. Tsai, King-Poul Zhu, Ying-Cheng Chu, S. Chiu","doi":"10.1109/ESSDER.2004.1356584","DOIUrl":null,"url":null,"abstract":"An InP/InGaAs /spl delta/-doped pnp heterojunction bipolar transistor (HBT) has been successfully fabricated and demonstrated for the first time. The addition of a /spl delta/-doped sheet between two undoped spacer layers more effectively eliminates the potential spike at the emitter-base junction, lowers the emitter-collector offset voltage, and increases the effective barrier for electrons, simultaneously. A maximum current gain of 50 and a low offset voltage of 70 mV are obtained, respectively. To our knowledge, the offset voltage of the studied device is the best reported for InP/InGaAs pnp HBTs.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"165 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Investigation of InP/InGaAs pnp /spl delta/-doped heterojunction bipolar transistor\",\"authors\":\"J. Tsai, King-Poul Zhu, Ying-Cheng Chu, S. Chiu\",\"doi\":\"10.1109/ESSDER.2004.1356584\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An InP/InGaAs /spl delta/-doped pnp heterojunction bipolar transistor (HBT) has been successfully fabricated and demonstrated for the first time. The addition of a /spl delta/-doped sheet between two undoped spacer layers more effectively eliminates the potential spike at the emitter-base junction, lowers the emitter-collector offset voltage, and increases the effective barrier for electrons, simultaneously. A maximum current gain of 50 and a low offset voltage of 70 mV are obtained, respectively. To our knowledge, the offset voltage of the studied device is the best reported for InP/InGaAs pnp HBTs.\",\"PeriodicalId\":287103,\"journal\":{\"name\":\"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)\",\"volume\":\"165 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-11-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDER.2004.1356584\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDER.2004.1356584","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

首次成功制备并演示了InP/InGaAs /spl δ /掺杂pnp异质结双极晶体管(HBT)。在两个未掺杂的间隔层之间添加a/ spl δ /掺杂片，更有效地消除了发射极-基极结处的电位尖峰，降低了发射极-集电极的偏置电压，同时增加了电子的有效势垒。最大电流增益为50，低失调电压为70毫伏。据我们所知，所研究器件的偏置电压是InP/InGaAs pnp HBTs的最佳报道。

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Investigation of InP/InGaAs pnp /spl delta/-doped heterojunction bipolar transistor

An InP/InGaAs /spl delta/-doped pnp heterojunction bipolar transistor (HBT) has been successfully fabricated and demonstrated for the first time. The addition of a /spl delta/-doped sheet between two undoped spacer layers more effectively eliminates the potential spike at the emitter-base junction, lowers the emitter-collector offset voltage, and increases the effective barrier for electrons, simultaneously. A maximum current gain of 50 and a low offset voltage of 70 mV are obtained, respectively. To our knowledge, the offset voltage of the studied device is the best reported for InP/InGaAs pnp HBTs.

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Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)

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