Analysis of the back gate effect on the breakdown behaviour of SOI LDMOS transistors

Abstract

This work investigates the impact of the back gate bias on the drain breakdown behaviour of lateral high voltage SOI transistors with thick epitaxial layers. For the first time, a detailed discussion is presented giving more insight into the physical mechanisms taking place in smart power SOI devices. The results show that five different breakdown mechanisms must be considered. An analytical model that takes the back gate bias and the device parameters into account is presented and verified with a 0.8 /spl mu/m 80 V SOI smart power technology.