Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)最新文献_第2页

Time-dependent dielectric breakdown of HfAlOx/SiON gate dielectric hhfalox /SiON栅介质的随时间介电击穿

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356496

K. Torii, T. Kawahara, R. Mitsuhashi, H. Ohji, A. Mutoh, S. Miyazaki, H. Kitajima, T. Arikado

引用次数: 0

Perspective of FinFETs for analog applications 模拟应用的finfet展望

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356489

V. Kilchytska, N. Collaert, R. Rooyackers, D. Lederer, J. Raskin, D. Flandre

引用次数: 55

Electrical analysis on the drain current of the ultra shallow junction by laser annealing 激光退火对超浅结漏极电流的电学分析

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356509

Soo-jin Hong, Young Pil Kim, J. Heo, Gook-Hyun Yon, G. H. Buh, Y. Shin, U. Chung, J. Moon

引用次数: 1

Self-aligned recessed source/drain ultra-thin body SOI MOSFET technology 自对准嵌入式源/漏极超薄体SOI MOSFET技术

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356549

Zhikuan Zhang, S. Zhang, M. Chan

引用次数: 1

Physical modeling and prediction of the matching properties of MOSFETs mosfet匹配特性的物理建模与预测

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356522

J. Croon, S. Decoutere, W. Sansen, H. Maes

引用次数: 33

Work function stability of thermal ALD Ta(Si)N gate electrodes on HfO/sub 2/ [CMOS device applications] 热ALD Ta(Si)N栅极在HfO/sub / [CMOS器件应用]上的功函数稳定性

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356494

J. Hooker, N. Pérez, P. Alén, M. Ritala, M. Leskela, F. Roozeboom, J.G.M. van Berkurn, E. Naburgh, F.C. van den Heuvel, J. Maes

引用次数: 0

Off current adjustment in ultra-thin SOI MOSFETs 超薄SOI mosfet的关断电流调节

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356550

J. Hartwich, L. Dreeskornfeld, F. Hofmann, J. Kretz, E. Landgraf, R. J. Luyken, M. Specht, M. Stadele, T. Schulz, W. Rosner, L. Risch

引用次数: 3

Channel engineering towards a full low temperature process solution for the 45 nm technology node [NMOS transistors] 面向45纳米技术节点[NMOS晶体管]的全低温工艺解决方案的通道工程

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356530

S. Severi, K. Henson, R. Lindsay, B. Pawlak, K. De Meyer

引用次数: 2

Electrical characterization and mechanical modeling of process induced strain in 65 nm CMOS technology 65纳米CMOS工艺诱发应变的电学表征和力学建模

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356508

C. Ortolland, S. Orain, J. Rosa, P. Morin, F. Arnaud, M. Woo, A. Poncet, P. Stolk

引用次数: 17

Ge deep sub-micron pFETs with etched TaN metal gate on a high-k dielectric, fabricated in a 200mm silicon prototyping line 在高k介电介质上蚀刻TaN金属栅极的Ge深亚微米pfet，在200mm硅原型生产线上制造

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356521

B. de Jaeger, M. Houssa, A. Satta, S. Kubicek, P. Verheyen, J. Van Steenbergen, J. Croon, B. Kaczer, S. Van Elshocht, A. Delabie, E. Kunnen, E. Sleeckx, I. Teerlinck, R. Lindsay, T. Schram, T. Chiarella, R. Degraeve, T. Conard, J. Poortmans, G. Winderickx, W. Boullart, M. Schaekers, P. Mertens, M. Caymax, W. Vandervorst, E. Van Moorhem, S. Biesemans, K. De Meyer, L. Ragnarsson, S. Lee, G. Kota, G. Raskin, P. Mijlemans, J. Autran, V. Afanas’ev, A. Stesmans, M. Meuris, M. Heyns

{"title":"Ge deep sub-micron pFETs with etched TaN metal gate on a high-k dielectric, fabricated in a 200mm silicon prototyping line","authors":"B. de Jaeger, M. Houssa, A. Satta, S. Kubicek, P. Verheyen, J. Van Steenbergen, J. Croon, B. Kaczer, S. Van Elshocht, A. Delabie, E. Kunnen, E. Sleeckx, I. Teerlinck, R. Lindsay, T. Schram, T. Chiarella, R. Degraeve, T. Conard, J. Poortmans, G. Winderickx, W. Boullart, M. Schaekers, P. Mertens, M. Caymax, W. Vandervorst, E. Van Moorhem, S. Biesemans, K. De Meyer, L. Ragnarsson, S. Lee, G. Kota, G. Raskin, P. Mijlemans, J. Autran, V. Afanas’ev, A. Stesmans, M. Meuris, M. Heyns","doi":"10.1109/ESSDER.2004.1356521","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356521","url":null,"abstract":"We report for the first time on deep sub-micron Ge pFETs with physical gate lengths down to 0.151 /spl mu/m. The devices are made using a silicon-like process flow, with a directly etched gate stack consisting of TaN gate on an ALD or MOCVD HfO/sub 2/ dielectric. Promising drive currents are found. Various issues such as the severe short channel effects (SCE), the increased diode leakage compared to Si and the high amount of interface states (N/sub it/) are addressed. The need for an alternative Ge substrate pre-treatment and subsequent high-k gate dielectric deposition to push EOT values below 1 nm is illustrated.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"2011 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121545564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11