Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)最新文献

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Evaluation of strain-induced mobility variation in TiN metal gate SOI n-MOSFETs TiN金属栅极SOI n- mosfet中应变诱导迁移率变化的评价
T. Guillaume, M. Mouis, S. Maitrejean, A. Poncet, M. Vinet, S. Deleonibus
{"title":"Evaluation of strain-induced mobility variation in TiN metal gate SOI n-MOSFETs","authors":"T. Guillaume, M. Mouis, S. Maitrejean, A. Poncet, M. Vinet, S. Deleonibus","doi":"10.1109/ESSDER.2004.1356572","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356572","url":null,"abstract":"In this paper, the influence of the strain induced by a TiN metal gate in the channel of n-MOS SOI transistors is investigated. Mechanical simulation has been used to calculate the strain components, which are found to show strong variations near the gate edge and a rather constant level under the gate. The influence on electron mobility has been calculated using the deformation potential theory, in its general formulation, as channel strain is neither purely biaxial nor uniaxial. It is found that electron mobility is more degraded by TiN-induced strain as the gate length becomes smaller. However, this degradation can be maintained below 10% for a [110]-oriented channel, provided that the residual stress in the 10 nm TiN layer is smaller than about 2.5 GPa.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125531719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Failure rate predictions for 0.35 /spl mu/m Flash EEPROM memories from accelerated read disturb tests 从加速读干扰测试中预测0.35 /spl mu/m闪存EEPROM存储器的故障率
T. Vermeulen, T. Yao, A. Lowe, P. Cacharelis, R. Degraeve, J. van Houdt
{"title":"Failure rate predictions for 0.35 /spl mu/m Flash EEPROM memories from accelerated read disturb tests","authors":"T. Vermeulen, T. Yao, A. Lowe, P. Cacharelis, R. Degraeve, J. van Houdt","doi":"10.1109/ESSDER.2004.1356541","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356541","url":null,"abstract":"Anomalous stress-induced leakage current (SILC) through the tunnel oxide is one of the major reliability problems limiting the lifetime of Flash EEPROM memory in the 0.35 /spl mu/m generation. The charge loss from the floating gate (FG) through the tunnel oxide under accelerated read disturb conditions is modelled with a statistical percolation model. The analysis allows extraction of the oxide trap density (Dot) as a function of the number of program/erase (P/E) cycles and a bit failure rate (BFR) prediction. For a typical tunnel oxide in 0.35 /spl mu/m Flash memory, the BFR due to read disturb is low in the first two years and reaches a steady state regime afterwards. Both Dot and BFR are expressed as a function of the number of P/E cycles by means of a power law. The analysis allows prediction of the read-disturb lifetime of Flash memory for a given tunnel oxide.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116756716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Gate-capacitance extraction from RF C-V measurements [MOS device applications] 射频C-V测量中的门电容提取[MOS器件应用]
G. Sasse, R. de Kort, J. Schmitz
{"title":"Gate-capacitance extraction from RF C-V measurements [MOS device applications]","authors":"G. Sasse, R. de Kort, J. Schmitz","doi":"10.1109/ESSDER.2004.1356501","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356501","url":null,"abstract":"In this work, a full two-port analysis of an RF C-V measurement set-up is given. This two-port analysis gives insight on the limitations of the commonly used gate capacitance extraction, based on the Y/sub 11/ parameter of the device. It is shown that the parasitics of the device can disturb the extracted gate capacitance and a new extraction scheme, based on the Z-matrix, is introduced that eliminates the effect of these parasitics. Measurement results prove the validity of this new extraction scheme, under different conditions.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114900286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Thermal scaling of ultra-thin SOI: reduced resistance at low temperature RTA 超薄SOI的热结垢:降低低温RTA电阻
Jong-Heon Yang, Jihun Oh, K. Im, I. Baek, C. Ahn, Jonghyurk Park, W. Cho, Seongjae Lee
{"title":"Thermal scaling of ultra-thin SOI: reduced resistance at low temperature RTA","authors":"Jong-Heon Yang, Jihun Oh, K. Im, I. Baek, C. Ahn, Jonghyurk Park, W. Cho, Seongjae Lee","doi":"10.1109/ESSDER.2004.1356512","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356512","url":null,"abstract":"This paper explores the effect of silicon-on-insulator (SOI) thickness scaling on its electrical properties. It is observed, for the first time, that the sheet resistance of ultra-thin SOI is lower than that of thick SOI under the same conditions of plasma doping and thermal annealing at low RTA temperature. This shows that dopant profile distribution and activation efficiency are different with different SOI thickness and different RTA temperature. In this work, we investigated the sheet resistance of SOI and made a comparative study of change in drain saturation current of a long channel FD SOI-MOSFET, fabricated with various SOI thickness and RTA temperatures, for the understanding of thermal scaling of ultra-thin SOI.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127460772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Experimental evidence and statistical modeling of cooperating defects in stressed oxides [FLASH memory example] 应力氧化物中协同缺陷的实验证据和统计建模[FLASH存储器实例]
F. Driussi, D. Esseni, L. Selmi, M. van Duuren, F. Widdershoven
{"title":"Experimental evidence and statistical modeling of cooperating defects in stressed oxides [FLASH memory example]","authors":"F. Driussi, D. Esseni, L. Selmi, M. van Duuren, F. Widdershoven","doi":"10.1109/ESSDER.2004.1356526","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356526","url":null,"abstract":"This work reports experimental data of stress induced leakage current (SILC) extracted from large FLASH cell arrays that indicate the possible presence of two types of defects in the stressed tunnel oxides. In order to support this interpretation, both an analytical and a numerical analysis of the generation and of the current conduction of cooperating defects in large arrays of cells have been developed. Our results demonstrate that the average number of two cooperating defects increases quadratically with the average number of single defects. This is in agreement with the experimental observation that the average number of defects per cell exhibits a super-linear dependence on the duration of the stress, for heavy stress conditions. The numerical simulations qualitatively reproduce all the main features of the experiments in the memory array, thus confirming the interpretation based on cooperating defects.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126139953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Influence of metal gate materials and processing on planar CMOS device characteristics with high-k gate dielectrics 金属栅极材料及工艺对高k栅极介质平面CMOS器件特性的影响
P. Majhi, C. Young, G. Bersuker, H. Wen, G.A. Brown, B. Foran, R. Choi, P. Zeitzoff, H. Huff
{"title":"Influence of metal gate materials and processing on planar CMOS device characteristics with high-k gate dielectrics","authors":"P. Majhi, C. Young, G. Bersuker, H. Wen, G.A. Brown, B. Foran, R. Choi, P. Zeitzoff, H. Huff","doi":"10.1109/ESSDER.2004.1356520","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356520","url":null,"abstract":"Scaled CMOS transistors with several types of metal gates on hafnium based high-k dielectrics were processed and studied to understand the influence of metal gates on device characteristics. The different metal gates that were comparatively studied include (a) TiN processed by ALD and PVD, and (b) PVD processed TaSiN and a multilayer HfN/Ta/TiN stack. From comprehensive electrical and nanostructural characterization, it was concluded that the differences in the properties of the devices, with ALD TiN gate electrodes compared to PVD TiN were due to the presence of the additional process grown interfacial oxide layer in the former samples. When comparing the TaSiN and multilayer HfN/Ta/TiN stacks, it was noted that the variation in device characteristics could be explained by the higher amount of nitrogen pile up at the high-k-Si interface for the multilayer metal stack. In all cases, the influence of processing on the nanostructure was addressed and a preliminary understanding of the processing-structure-property interrelationship is presented.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125989214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
High resolution two-dimensional carrier profiling on sub-100nm silicon nano-devices using scanning spreading resistance microscopy 扫描扩展电阻显微镜在亚100nm硅纳米器件上的高分辨率二维载流子分析
P. Eyben, H. Fukutome, D. Álvarez, W. Vandervorst
{"title":"High resolution two-dimensional carrier profiling on sub-100nm silicon nano-devices using scanning spreading resistance microscopy","authors":"P. Eyben, H. Fukutome, D. Álvarez, W. Vandervorst","doi":"10.1109/ESSDER.2004.1356498","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356498","url":null,"abstract":"This work presents the recent progress in scanning spreading resistance microscopy( SSRM) capabilities highlighting enhanced spatial resolution (<5 nm) and excellent concentration sensitivity (<20%). The latter is demonstrated through the analysis of three carrier profiling applications i.e. the calibration of process simulations for a 90 nm n-MOS technology, the determination of the impact of nitridation on the lateral diffusion in a 40 nm n-MOS technology and the study of activation problems in SPER-anneals of shallow implants.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128946581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new approach to the self-consistent solution of the Schrodinger-Poisson equations in nanowire MOSFETs 纳米线mosfet中薛定谔-泊松方程自洽解的新方法
E. Gnani, S. Reggiani, M. Rudan, G. Baccarani
{"title":"A new approach to the self-consistent solution of the Schrodinger-Poisson equations in nanowire MOSFETs","authors":"E. Gnani, S. Reggiani, M. Rudan, G. Baccarani","doi":"10.1109/ESSDER.2004.1356518","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356518","url":null,"abstract":"In this work, we investigate the electrostatics of fully-depleted cylindrical nanowire (CNW) MOSFETs accounting for quantum effects and, in doing so, we propose a new approach for the self-consistent solution of the Schrodinger-Poisson equations based on a rigorous time-independent perturbation approach. The strength of this method is that the Schrodinger equation is solved in a semi-analytical form, thus eliminating discretization errors and providing very accurate energy eigenvalues and eigenfunctions: furthermore, the computation time is cut down by an order of magnitude. A major result of this investigation is that the ON/OFF current ratio increases as the diameter of the CNW-MOSFET is scaled down. This makes them good candidates for an advanced low-leakage CMOS technology. The above technique is finally used to investigate the influence of high-/spl kappa/ gate dielectrics on the electrostatics of CNW-MOSFETs, indicating that an improved performance is achieved, though not as large as one would expect from the /spl kappa/ ratio.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124673746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Electrical characterization of partially insulated MOSFETs with buried insulators under source/drain regions 源/漏区埋地绝缘体部分绝缘mosfet的电学特性
C. Oh, K. Yeo, Min Sang Kim, Chang-Sub Lee, D. Choi, Sung Hwan Kim, S. Lee, Sung-min Kim, Jung-dong Choe, Yong Kyu Lee, E. Yoon, Ming Li, S. Suk, Dong-Won Kim, Donggun Park, Kinam Kim
{"title":"Electrical characterization of partially insulated MOSFETs with buried insulators under source/drain regions","authors":"C. Oh, K. Yeo, Min Sang Kim, Chang-Sub Lee, D. Choi, Sung Hwan Kim, S. Lee, Sung-min Kim, Jung-dong Choe, Yong Kyu Lee, E. Yoon, Ming Li, S. Suk, Dong-Won Kim, Donggun Park, Kinam Kim","doi":"10.1109/ESSDER.2004.1356532","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356532","url":null,"abstract":"In this article, we evaluated the structural merits of a partially insulated MOSFET (PiFET), for ultimate scaling of planar MOSFETs, through simulation and fabrication. The newly fabricated PiFET showed outstanding short channel effect (SCE) immunity and off-current characteristics over the conventional MOSFET, resulting from a self-induced halo region, self-limiting S/D shallow junction, and reduced junction area due to PiOX layer formation. Thus, the PiFET can be an attractive alternative for ultimate scaling of planar MOSFETs.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131181297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
The electro-thermal Smoothie database model for LDMOS devices LDMOS器件的电热Smoothie数据库模型
V. Cuoco, W. Neo, M. Spirito, O. Yanson, N. Nenadovic, L. D. de Vreede, H. Jos, J. Burghartz
{"title":"The electro-thermal Smoothie database model for LDMOS devices","authors":"V. Cuoco, W. Neo, M. Spirito, O. Yanson, N. Nenadovic, L. D. de Vreede, H. Jos, J. Burghartz","doi":"10.1109/ESSDER.2004.1356590","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356590","url":null,"abstract":"In this paper, we present the electro-thermal (ET) extension of the Smoothie database model for LDMOS devices together with its experimental verification. For the DC verification, the drain current was measured both in continuous mode and under isothermal conditions at different temperatures. In the RF large-signal verification, we used realistic loading conditions for the LDMOS devices while providing two-tone as well as IS-95 CDMA test conditions. With the aid of the above, thermal memory effects were studied by monitoring the device linearity versus tone spacing. In all the experiments, Smoothie demonstrated an excellent agreement with the measured results.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115399746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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