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Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)最新文献

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Characterization of Vt instability in hafnium based dielectrics by pulse gate voltage techniques [CMOS device applications] 脉冲栅电压技术表征铪基介电体Vt不稳定性[CMOS器件应用]
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356495
G. Ribes, M. Muller, S. Bruyère, D. Roy, M. Denais, V. Huard, T. Skotnicki, G. Ghibaudo
{"title":"Characterization of Vt instability in hafnium based dielectrics by pulse gate voltage techniques [CMOS device applications]","authors":"G. Ribes, M. Muller, S. Bruyère, D. Roy, M. Denais, V. Huard, T. Skotnicki, G. Ghibaudo","doi":"10.1109/ESSDER.2004.1356495","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356495","url":null,"abstract":"The transient threshold voltage instabilities occurring in CMOS devices in high-k oxide are considered as one of the major reliability issues opposing their successful integration. In this paper, we present an improved pulsed gate voltage technique for the characterization and the physical analysis of these phenomena. Based on the experimental observations of the trapping and detrapping kinetics, we determine the underlying physical mechanism and develop a new approach enabling the extraction of the energy distribution of the traps, aiming at the physical interpretation of their origin.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128271405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Electrostatic effect of localised charge in dual bit memory cells with discrete traps 具有离散陷阱的双比特存储单元中局部电荷的静电效应
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356536
L. Perniola, S. Bernardini, G. Iannaccone, B. De Salvo, G. Ghibaudo, P. Masson, C. Gerardi
{"title":"Electrostatic effect of localised charge in dual bit memory cells with discrete traps","authors":"L. Perniola, S. Bernardini, G. Iannaccone, B. De Salvo, G. Ghibaudo, P. Masson, C. Gerardi","doi":"10.1109/ESSDER.2004.1356536","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356536","url":null,"abstract":"In this paper, the electrostatic impact of channel hot electron (CHE) injection in discrete-trap memories is quantitatively addressed. The dual bit behavior of the transfer characteristics during forward and reverse read of a written cell is thoroughly analysed with the help of an analytical model. Such a model allows, for the first time, to estimate the effective charged portion of the discrete storage layer, L/sub 2/, and the quantity of electrons, Q, injected in the trapping sites from the experimental parameters of the I/sub d/-V/sub g/ characteristics, the reverse-forward threshold voltage shift /spl Delta/V/sub RF/, and the total threshold voltage shift /spl Delta/V/sub tot/. The viability of this model is confirmed with tests performed on nanocrystal memories, under different bias conditions. These results are confirmed with the help of a 2D drift-diffusion commercial code (ATLAS-SILVACO).","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124054305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrical characterization and modelling of high-performance SON DG MOSFETs 高性能SON - DG - mosfet的电特性和建模
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356567
S. Harrison, D. Munteanu, U. Autran, A. Cros, R. Cerutti, T. Skotnicki
{"title":"Electrical characterization and modelling of high-performance SON DG MOSFETs","authors":"S. Harrison, D. Munteanu, U. Autran, A. Cros, R. Cerutti, T. Skotnicki","doi":"10.1109/ESSDER.2004.1356567","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356567","url":null,"abstract":"The electrical performances of highly scaled double-gate (DG) MOS transistors fabricated using a silicon-on-nothing (SON) process are presented. Very high drive current, high immunity to short-channel effects and perfect electrostatic integrity are obtained for ultra-thin and ultra-short devices, with silicon thicknesses down to 10 nm and channel lengths down to 30 nm. In addition, a dedicated compact modeling of the threshold voltage is proposed, taking into account short-channel effects, quantum mechanical confinement effects and temperature dependence. Finally, the impact of these confinement effects and ballistic transport on the operation of such ultimate devices is investigated using 2D quantum-mechanical simulations.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"CE-23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126542895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A new substrate current free nLIGBT for junction isolated technologies 一种用于结隔离技术的新型衬底无电流光源
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356591
B. Bakeroot, J. Doutreloigne, P. Moens
{"title":"A new substrate current free nLIGBT for junction isolated technologies","authors":"B. Bakeroot, J. Doutreloigne, P. Moens","doi":"10.1109/ESSDER.2004.1356591","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356591","url":null,"abstract":"This paper presents a new lateral insulated gate bipolar transistor (LIGBT) for junction isolated technologies, the key property of which is a vertical isolation structure consisting of two buried layers on top of each other. This structure not only allows the suppression of substrate currents, it also yields an nLIGBT that can be used as a high-side switch. The proposed nLIGBT is introduced in an existing 80 V smart power technology without the costly need of defining new layers. It has a forward biased safe operating area (FBSOA) comparable to the DMOS devices in this technology and it can compete with DMOS devices when used as a large driver. Together with an equivalent circuit, two dimensional simulation has been used to verify the device's performance.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132063730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Determination of band-gap narrowing in heavily doped n-type GaAs and n-type GaInP from solar cell performance 从太阳能电池性能测定重掺杂n型GaAs和n型GaInP的带隙缩小
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356553
M. Ghannam, A. Al Omar, G. Flamand, N. Posthuma, J. Poortmans, R. Mertens
{"title":"Determination of band-gap narrowing in heavily doped n-type GaAs and n-type GaInP from solar cell performance","authors":"M. Ghannam, A. Al Omar, G. Flamand, N. Posthuma, J. Poortmans, R. Mertens","doi":"10.1109/ESSDER.2004.1356553","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356553","url":null,"abstract":"Band-gap narrowing (BGN) is determined in heavily doped n-type GaAs and n-type Ga/sub 0.5/In/sub 0.5/P from experimental pn junction solar cell performance. A BGN of 82 meV and of 17 meV is determined in GaAs with an n-type doping concentration of 2/spl times/10/sup 18//cm/sup 3/ and 10/sup 17//cm/sup 3/, respectively, and an average 95 meV BGN is determined in Ga/sub 0.5/In/sub 0.5/P with an n-type doping concentration of 3/spl times/10/sup 18//cm/sup 3/. These values agree well with theoretical predictions of a recent model applied to n-type GaAs and adapted here for Ga/sub 0.5/In/sub 0.5/P.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"17 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132365048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Plasma process induced damage during via etching on PDMOS transistors 等离子体工艺在经孔刻蚀PDMOS晶体管过程中引起损伤
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356527
P. Coppens, T. Colpaert, K. Dhondt, P. Bruneel, E. De Wade
{"title":"Plasma process induced damage during via etching on PDMOS transistors","authors":"P. Coppens, T. Colpaert, K. Dhondt, P. Bruneel, E. De Wade","doi":"10.1109/ESSDER.2004.1356527","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356527","url":null,"abstract":"This paper describes the threshold voltage shift observed on a floating PDMOS transistor, made in a 0.7 /spl mu/m compatible CMOS process. It is shown that this shift was caused by plasma induced damage. Positive charges introduced during the via etching are trapped in the gate of the PDMOS device. An explanation is also provided why the threshold voltage shift was mainly observed on this particular device. The plasma damage can be avoided by improving the via etch uniformity. It has also been proven that by extending the sinter time we were able to anneal out oxide trapped charges, hence making the process more immune to this type of damage.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123382164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Advanced SEU engineering using a triple well architecture [CMOS SRAM] 采用三井结构的先进SEU工程[CMOS SRAM]
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356566
H. Puchner, Y.Z. Xu, D. Radaelli
{"title":"Advanced SEU engineering using a triple well architecture [CMOS SRAM]","authors":"H. Puchner, Y.Z. Xu, D. Radaelli","doi":"10.1109/ESSDER.2004.1356566","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356566","url":null,"abstract":"A triple well scheme has been implemented on an 18 Mbit fast synchronous SRAM by using a high energy implant to evaluate its impact on the alpha-particle induced accelerated soft error rate (ASER). The device uses a single poly, 0.15 /spl mu/m CMOS process. The SEU performance of the test vehicle shows that the advantage of the triple well isolation and better SEU performance can only be achieved by a proper design of the wells. There is a trade off in the NMOS and PMOS region for the triple well scheme. In general, it improves in the NMOS area but degrades in the PMOS area due to the increased collection volume for holes in the PMOS area. The effectiveness of the triple well architecture depends on balancing the well design and tapping scheme trade offs.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124792970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Flexible semiconductor devices: fingerprint sensor and electrophoretic display on plastic [TFT based] 柔性半导体器件:塑料指纹传感器和电泳显示[基于TFT]
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356551
H. Takao, M. Miyasaka, H. Kawai, H. Hara, A. Miyazaki, T. Kodaira, S. Tam, S. Inoue, T. Shimoda
{"title":"Flexible semiconductor devices: fingerprint sensor and electrophoretic display on plastic [TFT based]","authors":"H. Takao, M. Miyasaka, H. Kawai, H. Hara, A. Miyazaki, T. Kodaira, S. Tam, S. Inoue, T. Shimoda","doi":"10.1109/ESSDER.2004.1356551","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356551","url":null,"abstract":"We are on the brink of a new era in flexible semiconductor devices. Outstanding devices, such as a fingerprint sensor (FPS) and an active-matrix electrophoretic display (AM-EPD), are fabricated on a plastic sheet, using thin film transistor (TFT) technology. The devices are first fabricated on a glass substrate with high-performance low-temperature processed polycrystalline silicon (LTPS) TFTs, then later transferred onto a plastic sheet. The FPS and AM-EPD devices on plastic are presented in this paper as examples of flexible semiconductor devices.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123961944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Analysis and application of energy capability characterization methods in power MOSFETs 功率mosfet能量性能表征方法的分析与应用
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356589
G. Van den bosch, P. Moens, P. Gassot, D. Wojciechowski, G. Groeseneken
{"title":"Analysis and application of energy capability characterization methods in power MOSFETs","authors":"G. Van den bosch, P. Moens, P. Gassot, D. Wojciechowski, G. Groeseneken","doi":"10.1109/ESSDER.2004.1356589","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356589","url":null,"abstract":"A theoretical and experimental comparison is made between different energy capability (EC) characterization methods in power MOSFETs. In traditional clamped inductive switching (CIS) the measurement conditions are difficult to control independently. Moreover, theoretical analysis suggests that the CIS results are not unique but depend on measurement circuit parameters. An alternative method uses rectangular power pulses. Various implementations have been considered and the resulting energy capability data have been shown to match well with one another and with the CIS data. The influence on EC of a thick Cu layer covering the power transistor is demonstrated.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122856591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Double gate silicon-on-insulator transistors: n/sup +/-n/sup +/ gate versus n/sup +/-p/sup +/ gate configuration 双栅绝缘体上硅晶体管:n/sup +/-n/sup +/栅极与n/sup +/-p/sup +/栅极配置
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356517
F. Gámiz, J. Roldán, A. Godoy, F. Jiménez-Molinos
{"title":"Double gate silicon-on-insulator transistors: n/sup +/-n/sup +/ gate versus n/sup +/-p/sup +/ gate configuration","authors":"F. Gámiz, J. Roldán, A. Godoy, F. Jiménez-Molinos","doi":"10.1109/ESSDER.2004.1356517","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356517","url":null,"abstract":"We have studied electron mobility behavior in asymmetric double-gate silicon on insulator (DGSOI) inversion layers, and compared it to the mobility in symmetric double-gate silicon on insulator devices. The electron mobility curves in asymmetric DGSOI devices are shown to be considerably below the mobility curves corresponding to symmetric devices, in the whole range of silicon thicknesses. We show that the lack of symmetry in the asymmetric DGSOI structure produces the loss of the volume inversion effect. In addition, we show that as the silicon thickness is reduced, the conduction effective mass of electrons in asymmetric devices is lower than that in the symmetric case, but that the greater confinement of electrons in the former case produces a stronger increase in the phonon scattering rate, and in the surface roughness scattering rate.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115587563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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