Plasma process induced damage during via etching on PDMOS transistors

Abstract

This paper describes the threshold voltage shift observed on a floating PDMOS transistor, made in a 0.7 /spl mu/m compatible CMOS process. It is shown that this shift was caused by plasma induced damage. Positive charges introduced during the via etching are trapped in the gate of the PDMOS device. An explanation is also provided why the threshold voltage shift was mainly observed on this particular device. The plasma damage can be avoided by improving the via etch uniformity. It has also been proven that by extending the sinter time we were able to anneal out oxide trapped charges, hence making the process more immune to this type of damage.