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Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)最新文献

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Reliability of embedded SONOS memories 嵌入式SONOS存储器的可靠性
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356543
R. van Schaijk, M. van Duuren, P. Goarin, W. Y. Mei, K. van der Jeugd
{"title":"Reliability of embedded SONOS memories","authors":"R. van Schaijk, M. van Duuren, P. Goarin, W. Y. Mei, K. van der Jeugd","doi":"10.1109/ESSDER.2004.1356543","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356543","url":null,"abstract":"In this work, arrays of two transistor (2T) and compact SONOS memory cells are presented together with an extensive reliability investigation. SONOS, which stands for semiconductor-oxide-nitride-oxide-semiconductor, is a non-volatile memory concept, which has recently regained strong attention because floating gate flash has reached its scaling limits. The better scaling perspective, together with the ease of integration in a base line CMOS process, makes SONOS an excellent candidate for embedded flash in future CMOS generations. This is especially true for the compact cell variant, which consists of a merged access gate (AG) and control gate (CG), giving extra advantages like smaller cell size and the reduction of short channel effects compared with the discrete two transistor variant.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126287291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Back-etched super-junction LDMOST on SOI SOI上背蚀刻超结LDMOST
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356502
S. Honarkhah, S. Nassif-Khalil, C. Salama
{"title":"Back-etched super-junction LDMOST on SOI","authors":"S. Honarkhah, S. Nassif-Khalil, C. Salama","doi":"10.1109/ESSDER.2004.1356502","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356502","url":null,"abstract":"Conventional super junction LDMOSTs (SJLDMOSTs), fabricated on an SOI substrate, suffer from low breakdown voltage due to substrate-depletion effects. In this work, a back etched SJLDMOST (BSJLDMOST) on SOI is proposed to overcome this problem by eliminating the silicon substrate under the device. The electrical characteristics of the BSJLDMOST on a 0.8 /spl mu/m SOI film were investigated. The device with 15.5 /spl mu/m of SJ region exhibits a breakdown voltage of 317 V, a specific on-resistance of 48.3 m/spl Omega/cm/sup 2/ and a charge on-resistance figure of merit of 4.1 /spl Omega/nC. To verify the back etching concept and the suppression of the substrate depletion effect, super-junction diodes (BSJDs) were implemented. These diodes feature a threefold improvement in breakdown voltage over conventional super junction diodes (SJDs) implemented without removing the silicon substrate on the back of the device. A discussion of how the BSJLDMOST can be optimized to break the silicon limit is also provided.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124045327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
Effect of high-k materials in the control dielectric stack of nanocrystal memories 高k材料对纳米晶存储器控制介电堆的影响
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356514
E. Spitale, D. Corso, I. Crupi, G. Nicotra, S. Lombardo, D. Deleruyelle, M. Gely, N. Buffet, B. De Salvo, C. Gerardi
{"title":"Effect of high-k materials in the control dielectric stack of nanocrystal memories","authors":"E. Spitale, D. Corso, I. Crupi, G. Nicotra, S. Lombardo, D. Deleruyelle, M. Gely, N. Buffet, B. De Salvo, C. Gerardi","doi":"10.1109/ESSDER.2004.1356514","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356514","url":null,"abstract":"In this paper, we studied program/erase characteristics by FN tunneling in Si nanocrystal memories. Starting from a very good agreement between experimental data and simulations in the case of a memory cell with a thin tunnel oxide, silicon dots as medium for charge storage, and a CVD silicon dioxide used as control dielectric, we present estimated values of the charge trapping when a high-k material is present in the control dielectric. We then show preliminary results of nanocrystal memories with control dielectric containing high-k materials.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125511237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Organic thin film transistors: a DC model for circuit simulation 有机薄膜晶体管:一种用于电路仿真的直流模型
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356578
L. Colalongo, F. Romano, Z. Vajna
{"title":"Organic thin film transistors: a DC model for circuit simulation","authors":"L. Colalongo, F. Romano, Z. Vajna","doi":"10.1109/ESSDER.2004.1356578","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356578","url":null,"abstract":"In this paper, a new analytical model for the DC current of organic thin-film transistors is presented. The model is based on the variable range hopping theory, i.e. thermally activated tunneling of carriers between localized states. It accurately accounts for below-threshold, linear and saturation operating conditions via a single formulation. Furthermore, the model does not require the explicit definition of the threshold and saturation voltages as input parameters, which are rather ambiguously defined. The model is also suitable for CAD applications.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"32 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125706870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Modeling of STI-induced stress phenomena in CMOS 90nm Flash technology CMOS 90nm Flash技术中sti诱导应力现象的建模
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356574
P. Fantini, G. Giuga, S. Schippers, A. Marmiroli, G. Ferrari
{"title":"Modeling of STI-induced stress phenomena in CMOS 90nm Flash technology","authors":"P. Fantini, G. Giuga, S. Schippers, A. Marmiroli, G. Ferrari","doi":"10.1109/ESSDER.2004.1356574","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356574","url":null,"abstract":"A non negligible layout sensitivity of MOSFETS electrical behavior has been recently observed in advanced CMOS technologies. Some efforts have been attempted to encapsulate this phenomenon in Spice-like simulation oriented models. In the present work, we suggest improvements to previously proposed approaches, after a critical discussion about them. An extensive characterization of CMOS 90 nm Flash memory technology is the support of our issues. Finally, simulation of prototype circuits shed some light on the impact of STI stress in IC design.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114213469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Injection-limited current in a polymeric heterojunction 聚合物异质结中的注入限制电流
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356580
T. van Woudenbergh, J. Wildeman, P. Blom
{"title":"Injection-limited current in a polymeric heterojunction","authors":"T. van Woudenbergh, J. Wildeman, P. Blom","doi":"10.1109/ESSDER.2004.1356580","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356580","url":null,"abstract":"This work describes the current over an interface between two different polymeric semiconductors. The interface barrier amounts to 0.7 to 1.0 eV, which is orders of magnitude larger than the thermal energy. It is demonstrated that the current across the interface is injection limited. Furthermore, it is observed that the electrical characteristics for such an organic-organic interface are completely different from those for a metal organic interface.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127724226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Self-consistent characterization of gate controlled diodes for CMOS technology monitoring 用于CMOS技术监测的门控二极管的自一致性表征
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356571
R. Sorge, P. Schley, K. Ehwald
{"title":"Self-consistent characterization of gate controlled diodes for CMOS technology monitoring","authors":"R. Sorge, P. Schley, K. Ehwald","doi":"10.1109/ESSDER.2004.1356571","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356571","url":null,"abstract":"We report a novel effective method for a comprehensive characterization of gate controlled diodes within an end of line CMOS process monitoring. The described technique is based on the simultaneous measurement of the gate current, the high frequency gate capacitance, and the drain current. It enables a rapid self-consistent determination of all relevant interface and near surface MOS parameters. In contrast to approaches described in the literature, the new method does not rely on the assumption of homogeneously doped samples. The practically relevant case of a doping profile in the near-surface device region is taken into account at the parameter extraction.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133131709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Device design for sub 90 nm MOSFETs for sample and hold circuits 用于样品和保持电路的sub - 90 nm mosfet器件设计
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356568
M. Gupta, J. Woo
{"title":"Device design for sub 90 nm MOSFETs for sample and hold circuits","authors":"M. Gupta, J. Woo","doi":"10.1109/ESSDER.2004.1356568","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356568","url":null,"abstract":"In this paper, we have extensively studied how different device parameters affect the constituents of sampling circuit performance metrics. As the MOSFET is scaled into the sub-90 nm regime, for ADCs using moderate sampling rate and high resolutions, the gate tunneling current not only severely degrades the droop rate but also affects the nonlinearity adversely. The effect of scaling on various trade-offs that exist among the metric constituents is also presented. These device guidelines can be used to improve the sample and hold operation to a fairly general degree.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132126230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
New methodologies of NBTI characterization eliminating recovery effects 消除恢复效应的NBTI表征新方法
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356540
M. Denais, V. Huard, C. Parthasarathy, G. Ribes, F. Perrier, N. Revil, A. Bravaix
{"title":"New methodologies of NBTI characterization eliminating recovery effects","authors":"M. Denais, V. Huard, C. Parthasarathy, G. Ribes, F. Perrier, N. Revil, A. Bravaix","doi":"10.1109/ESSDER.2004.1356540","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356540","url":null,"abstract":"This work gives new insights of negative bias temperature instability (NBTI) characterization methodologies in advanced CMOS technology. NBTI is well-known to seriously limit the circuit performances in p-channel MOSFETs, in relation to both interface trap generation and hole trapping in the gate oxide. Hole detrapping from oxide traps during electrical parameter extractions, also called a recovery phenomenon, is unanimously acknowledged to be the most critical phenomenon avoiding a proper characterization of the effective damage. We point out here new NBTI evaluation techniques using pulsed voltages on the gate and on the drain to characterize NBT degradation and quantify recovery effects in the usual methodology.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127134767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Gain and polaron absorption in electrically pumped single-layer organic laser diodes 电泵浦单层有机激光二极管的增益与极化子吸收
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356579
C. Pflumm, C. Karnutsch, M. Gerken, U. Lemmer
{"title":"Gain and polaron absorption in electrically pumped single-layer organic laser diodes","authors":"C. Pflumm, C. Karnutsch, M. Gerken, U. Lemmer","doi":"10.1109/ESSDER.2004.1356579","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356579","url":null,"abstract":"In this article, a model to calculate the modal gain in organic laser diode structures is presented. A single layer design is considered, to investigate the dependence of the gain on electron mobility and the thickness of the active layer. We show that unequal charge carrier mobilities are detrimental and that there is an optimum active layer thickness of d/spl ap/200 nm, when different devices are compared on the basis of power density. The calculated gain is 0.7/cm for a power density of P=50 kW/cm/sup 2/, neglecting all losses. Furthermore, the influence of absorption by polarons is quantified. We show that the cross section for this process has to be less than 4% of the cross section for stimulated emission in order to achieve net gain.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130277016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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