射频C-V测量中的门电容提取[MOS器件应用]

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI:10.1109/ESSDER.2004.1356501

G. Sasse, R. de Kort, J. Schmitz

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引用次数: 4

摘要

在这项工作中，给出了射频C-V测量装置的完整双端口分析。基于器件的Y/sub 11/参数，该双端口分析深入了解了常用栅极电容提取的局限性。结果表明，器件的寄生效应会干扰提取的栅极电容，提出了一种基于z矩阵的新型提取方案，消除了这些寄生效应的影响。实测结果证明了该提取方案在不同条件下的有效性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Gate-capacitance extraction from RF C-V measurements [MOS device applications]

In this work, a full two-port analysis of an RF C-V measurement set-up is given. This two-port analysis gives insight on the limitations of the commonly used gate capacitance extraction, based on the Y/sub 11/ parameter of the device. It is shown that the parasitics of the device can disturb the extracted gate capacitance and a new extraction scheme, based on the Z-matrix, is introduced that eliminates the effect of these parasitics. Measurement results prove the validity of this new extraction scheme, under different conditions.

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Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)

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