Influence of metal gate materials and processing on planar CMOS device characteristics with high-k gate dielectrics

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI:10.1109/ESSDER.2004.1356520

P. Majhi, C. Young, G. Bersuker, H. Wen, G.A. Brown, B. Foran, R. Choi, P. Zeitzoff, H. Huff

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引用次数: 8

Abstract

Scaled CMOS transistors with several types of metal gates on hafnium based high-k dielectrics were processed and studied to understand the influence of metal gates on device characteristics. The different metal gates that were comparatively studied include (a) TiN processed by ALD and PVD, and (b) PVD processed TaSiN and a multilayer HfN/Ta/TiN stack. From comprehensive electrical and nanostructural characterization, it was concluded that the differences in the properties of the devices, with ALD TiN gate electrodes compared to PVD TiN were due to the presence of the additional process grown interfacial oxide layer in the former samples. When comparing the TaSiN and multilayer HfN/Ta/TiN stacks, it was noted that the variation in device characteristics could be explained by the higher amount of nitrogen pile up at the high-k-Si interface for the multilayer metal stack. In all cases, the influence of processing on the nanostructure was addressed and a preliminary understanding of the processing-structure-property interrelationship is presented.

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金属栅极材料及工艺对高k栅极介质平面CMOS器件特性的影响

研究了几种金属栅极在高k介电介质上的比例化CMOS晶体管，了解了金属栅极对器件特性的影响。比较研究的不同金属栅极包括(a) ALD和PVD处理的TiN，以及(b) PVD处理的TaSiN和多层HfN/Ta/TiN堆栈。从全面的电学和纳米结构表征中，我们得出结论，与PVD TiN相比，ALD TiN栅极器件性能的差异是由于在前者样品中存在额外的工艺生长界面氧化层。当比较TaSiN和多层HfN/Ta/TiN堆叠时，我们注意到器件特性的变化可以解释为多层金属堆叠在高k- si界面处堆积了更多的氮。在所有情况下，处理对纳米结构的影响进行了讨论，并初步了解了处理-结构-性能之间的相互关系。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)

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