热ALD Ta(Si)N栅极在HfO/sub / [CMOS器件应用]上的功函数稳定性

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI:10.1109/ESSDER.2004.1356494

J. Hooker, N. Pérez, P. Alén, M. Ritala, M. Leskela, F. Roozeboom, J.G.M. van Berkurn, E. Naburgh, F.C. van den Heuvel, J. Maes

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引用次数: 0

摘要

研究了热原子层沉积法(ALD)沉积的Ta(Si)N薄膜作为先进CMOS器件的电位栅电极材料。在ALD厚度系列HfO/ sub2 /上，通过高频电容电压测量(HF-CV)测定了这些薄膜的功函数(/spl Phi//sub m/)。采用优化的脉冲序列，在400和500℃的温度下沉积薄膜，研究了Si含量分别为3%和8%的两种薄膜。两种Ta(Si)N薄膜的/spl Phi/ sub - m/均为4.7/spl plusmn/0.1 eV，经过高温热处理后，400/spl℃的沉积层具有更可靠的电气性能。

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Work function stability of thermal ALD Ta(Si)N gate electrodes on HfO/sub 2/ [CMOS device applications]

Ta(Si)N films deposited by thermal atomic layer deposition (ALD) have been investigated as potential gate electrode materials in advanced CMOS devices. The work function (/spl Phi//sub m/) of these films was determined by high-frequency capacitance-voltage measurements (HF-CV) on a thickness series of ALD HfO/sub 2/. Depositing films at 400 and 500/spl deg/C with an optimized pulse sequence, two films with Si content of 3 and 8 at%, respectively, were studied. Both Ta(Si)N films gave /spl Phi//sub m/ of 4.7/spl plusmn/0.1 eV, also, after high-temperature thermal treatment, with the 400/spl deg/C deposition giving more reliable electrical performance.

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Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)

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