65纳米CMOS工艺诱发应变的电学表征和力学建模

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI:10.1109/ESSDER.2004.1356508

C. Ortolland, S. Orain, J. Rosa, P. Morin, F. Arnaud, M. Woo, A. Poncet, P. Stolk

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引用次数: 17

摘要

本文研究了应变接触蚀刻停止层对65nm CMOS晶体管性能的影响。结果表明，氮化层可使NMOS和PMOS的驱动电流分别提高8.5%和6%。通过结合完整的电气分析，力学建模和量子模拟，我们详细了解了晶体管布局规则如何影响应变增强。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Electrical characterization and mechanical modeling of process induced strain in 65 nm CMOS technology

In this paper, we present a study of the effects of strained contact etch stop layer on 65 nm CMOS transistor performance. It is found that the nitride layer above the transistor can improve the transistor drive current by 8.5% for NMOS and 6% for PMOS. By combining a complete electrical analysis, mechanical modeling and quantum simulations, we have obtained a detailed understanding of how transistor layout rules influence the strain enhancements.

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Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)

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