sti诱导应力、逆窄宽度效应和统计V/sub TH/变化对120nm CMOS漏电流的影响

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI:10.1109/ESSDER.2004.1356573

C. Pacha, B. Martin, K. von Arnim, R. Brederlow, D. Schmitt-Landsiedel, P. Seegebrecht, J. Berthold, R. Thewes

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引用次数: 55

摘要

120nm CMOS技术中的漏电流取决于sti诱导应力(STIS)、逆窄宽效应(INWE)和统计阈值电压变化。在本文中，我们分析了这些效应对器件断流密度的栅极宽度依赖性的影响。提出了一个阈值电压模型来描述观察到的最小失电电流。当栅极宽度较大时，STIS主导器件行为，而当栅极宽度小于1 /spl mu/m时，INWE决定断开电流。统计阈值电压变化与最小尺寸的器件有关。

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Impact of STI-induced stress, inverse narrow width effect, and statistical V/sub TH/ variations on leakage currents in 120 nm CMOS

Leakage currents in 120 nm CMOS technology are dependent on STI-induced stress (STIS), inverse narrow-width effect (INWE), and statistical threshold voltage variations. In this paper, we analyze the impact of these effects on the gate-width dependence of the device off-current density. A threshold voltage model is proposed to describe the observed off-current minimum. STIS dominates the device behavior for large gate widths while INWE determines the off-current for gate widths below 1 /spl mu/m. Statistical threshold voltage variations are relevant for minimum-sized devices.

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Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)

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