Low power digital circuit design

Abstract

The paper describes approaches for achieving low power digital circuits. The approaches are classified from the standpoint of spatial granularity, temporal granularity and variable granularity. The trend is moving from coarse-grain to the finer grain to save more power with the higher engineering cost. The newer approach includes dynamic adaptive control of V/sub DD/ and V/sub TH/ at a block level. The paper also touches on low-power applications.