Phase-change memory technology for embedded applications

Abstract

A novel p-trench phase-change memory (PCM) cell and its integration with a MOSFET selector in a standard 0.18 /spl mu/m CMOS technology are presented. The high-performance capabilities of PCM cells are experimentally investigated and their application in embedded systems is discussed. Write times as low as 10 ns and 20 ns have been measured for the RESET and SET operation, respectively, still granting a 10/spl times/ read margin. The impact of the RESET pulse on PCH cell endurance has been also evaluated. Finally, cell distributions and first statistical endurance measurements on a 4 Mbit MOS demonstrator clearly assess the feasibility of the PCM technology.