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Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)最新文献

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Integrated circuits for the biology-to-silicon interface 用于生物硅接口的集成电路
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356477
R. Thewes, C. Paulus, M. Schienle, F. Hofmann, A. Frey, R. Brederlow, P. Schindler-Bauer, M. Augustyniak, M. Atzesberger, B. Holzapfl, M. Jenkner, B. Eversmann, G. Beer, M. Fritz, T. Haneder, H. Hanke
{"title":"Integrated circuits for the biology-to-silicon interface","authors":"R. Thewes, C. Paulus, M. Schienle, F. Hofmann, A. Frey, R. Brederlow, P. Schindler-Bauer, M. Augustyniak, M. Atzesberger, B. Holzapfl, M. Jenkner, B. Eversmann, G. Beer, M. Fritz, T. Haneder, H. Hanke","doi":"10.1109/ESSDER.2004.1356477","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356477","url":null,"abstract":"An overview is given of CMOS-based sensor and actuator chips for in-vitro applications in the biotechnology area. We address the challenges and the potential of the combination of solid-state circuits with the wet world of bio molecules and living cells. Basic biological operating principles, market considerations, extended CMOS processing issues, and concrete circuit examples are discussed.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127058462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Efficient simulation framework for circuit design with future device technologies [MOS structures] 面向未来器件技术的高效电路设计仿真框架[MOS结构]
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356570
R. Gottsche, T. Schulz, N. Bruls, W. Krautschneider
{"title":"Efficient simulation framework for circuit design with future device technologies [MOS structures]","authors":"R. Gottsche, T. Schulz, N. Bruls, W. Krautschneider","doi":"10.1109/ESSDER.2004.1356570","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356570","url":null,"abstract":"A simulation framework has been developed for fast and accurate calculation of MOS transistor characteristics. It is based on an optimized table model so that it can be run solely using experimental or simulated I-V data, i.e. without any time-consuming determination of model parameters. This model is designed in a very flexible manner, thus it can be used for advanced MOS structures, such as double-gate and FinFET transistors, as well. By this means, it facilitates the integration of a parameterized device technology directly into a conventional design flow to qualify circuits in the design space.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125422212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effects of wet cleaning treatment on dose of impurity after plasma doping 湿清洗处理对血浆掺杂后杂质剂量的影响
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356511
T. Sato, R. Higaki, H. Tamura, Y. Sasaki, B. Mizuno, K. Tsutsui, H. Iwai
{"title":"Effects of wet cleaning treatment on dose of impurity after plasma doping","authors":"T. Sato, R. Higaki, H. Tamura, Y. Sasaki, B. Mizuno, K. Tsutsui, H. Iwai","doi":"10.1109/ESSDER.2004.1356511","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356511","url":null,"abstract":"Plasma doping is a promising candidate to realize ultra shallow junctions for future small scale CMOS devices. Wet cleaning processes were investigated on shallow boron doped layers, formed by the plasma doping method, in this work. The three kinds of cleaning processes such as diluted HF, APM and SPM were used for as doped samples, and the loss of boron after thermal annealing between these cleaning processes was compared . It was found that the diluted HF cleaning exhibited a large decrease of boron dose while the SPM cleaning exhibited a suppression of loss of boron dose. It was speculated that inclusion of boron into the chemical oxide layer formed by the SPM treatment contributed to the suppression of loss of boron in the following annealing process.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125426879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Comparative analysis of basic transport properties in the inversion layer of bulk and SOI MOSFETs: a Monte-Carlo study 体型和SOI型mosfet反转层基本输运特性的比较分析:蒙特卡罗研究
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356554
L. Lucci, D. Esseni, P. Palestri, L. Selmi
{"title":"Comparative analysis of basic transport properties in the inversion layer of bulk and SOI MOSFETs: a Monte-Carlo study","authors":"L. Lucci, D. Esseni, P. Palestri, L. Selmi","doi":"10.1109/ESSDER.2004.1356554","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356554","url":null,"abstract":"A Monte-Carlo simulator for the quasi-2D electron gas in the inversion layer of bulk and SOI MOSFETs has been developed. The code has been used to validate the momentum-relaxation-time technique, commonly used to evaluate the low field mobility, pointing out the importance of inter-subband transitions in SOI devices. The high field transport properties in thin SOI MOSFETs have been investigated, showing for the first time that surface roughness scattering could have a strong impact on the saturation velocity whose value is significantly lower than the value reported for bulk silicon and bulk MOSFETs. On the other hand, the high energy carrier distribution is only weakly influenced by carrier quantization.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122979031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Analysis of substrate noise propagation in a lightly doped substrate [mixed-signal ICs] 轻掺杂衬底中衬底噪声传播分析[混合信号集成电路]
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356564
G. van der Plas, C. Soens, G. Vandersteen, P. Wambacq, S. Donnay
{"title":"Analysis of substrate noise propagation in a lightly doped substrate [mixed-signal ICs]","authors":"G. van der Plas, C. Soens, G. Vandersteen, P. Wambacq, S. Donnay","doi":"10.1109/ESSDER.2004.1356564","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356564","url":null,"abstract":"Analysis and simulation results of substrate noise in mixed-signal ICs on lightly doped substrates are difficult to bring in agreement with measurements, even for very simple structures. In this paper, substrate noise propagation in lightly doped p-type substrates is studied with a simple test structure. Our study reveals that the current flow is multi-dimensional, and that adjacent layout details (such as nwells and metal wires) influence the propagation between two contacts. The analysis has enabled its to match the measured S/sub 21/ propagation with a simulation model from DC (error<8%) up to 10 GHz with an overall error smaller than 3 dB. Insight in simple structures such as the one considered here, is valuable in improving the understanding of substrate noise in lightly doped substrates.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121746504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Requirements on CD and overlay for 200 GHz QSA SiGe:C HBTs 200ghz QSA SiGe:C hbt对CD和覆盖的要求
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356557
K. van Wichelen, L. Witters, S. Van Huylenbroeck, P. Leray, D. Laidler, E. Kunnen, S. Decoutere
{"title":"Requirements on CD and overlay for 200 GHz QSA SiGe:C HBTs","authors":"K. van Wichelen, L. Witters, S. Van Huylenbroeck, P. Leray, D. Laidler, E. Kunnen, S. Decoutere","doi":"10.1109/ESSDER.2004.1356557","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356557","url":null,"abstract":"In this paper, we investigate the sensitivity of the quasi self-alignment (QSA) architecture to CD variation and alignment, resulting in a set of requirements on lithography capability imposed by the electrical performance of the device. We show that these requirements can be met without difficulty using present-day step and scan tools, so long as some precautions are taken in terms of alignment strategy. We show that the base current, current gain and BV/sub EBO/ are the DC parameters of the HBT device most sensitive to misalignment.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117190859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Silicon oxide formation for TFTs using humid ozone-enriched gas ambient at low temperature 低温富臭氧潮湿气体环境下tft氧化硅的形成
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356552
P. N. Hai, S. Nishio, S. Horita
{"title":"Silicon oxide formation for TFTs using humid ozone-enriched gas ambient at low temperature","authors":"P. N. Hai, S. Nishio, S. Horita","doi":"10.1109/ESSDER.2004.1356552","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356552","url":null,"abstract":"Humid ozone-enriched ambient, created by bubbling (O/sub 3/+O/sub 2/) gas in H/sub 2/O or H/sub 2/O/sub 2/, enhanced the silicon oxide growth on a Si substrate at 250/spl deg/C. The film thickness was controllable with a high growth rate of 1.4 /spl Aring//min. The XPS data shows that the oxide layer on the Si(111) has the same transition layer structure as thermal SiO/sub 2/ film. By combination with a short-time treatment at higher temperature (below 500/spl deg/C), the electrical characteristics of SiO/sub 2/ thin films were improved. The operation of polycrystalline Si thin film transistors using this oxide film indicates that the new growth method is applicable for low-temperature device fabrication.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129003646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low temperature process flow optimisation for 65nm CMOS mixed-signal applications 65纳米CMOS混合信号应用的低温工艺流程优化
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356523
B. Duriez, P. Morin, B. Tavel, B. Froment, P. Gouraud, D. Roy, K. Rochereau, R. Difrenza, A. Margin, M. Denais, M. Bidaud, P. Stolk, M. Woo, F. Arnaud
{"title":"Low temperature process flow optimisation for 65nm CMOS mixed-signal applications","authors":"B. Duriez, P. Morin, B. Tavel, B. Froment, P. Gouraud, D. Roy, K. Rochereau, R. Difrenza, A. Margin, M. Denais, M. Bidaud, P. Stolk, M. Woo, F. Arnaud","doi":"10.1109/ESSDER.2004.1356523","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356523","url":null,"abstract":"In this work, a complete low temperature 65 nm process flow using a low-cost, conventional CMOS approach has been investigated. A significant global thermal budget reduction has been achieved (below 500/spl deg/C), especially for the spacer, silicide-protection and salicide modules. The introduction of new materials induced a great transistor performance enhancement in both the digital and analog/mixed-signal domains. The I/sub off/-I/sub on/ figure of merit has been improved by 20%, whereas the matching factors were reduced for both NMOS and PMOS transistors. This new optimized process flow satisfies the strict criteria of transistor reliability.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128318508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Dynamic latchup study using transmission line pulses and picosecond imaging circuit analysis [CMOS IC latchup] 传输线脉冲动态闭锁研究及皮秒成像电路分析[CMOS IC闭锁]
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356525
F. Stellari, A. Weger, P. Song, M. McManus
{"title":"Dynamic latchup study using transmission line pulses and picosecond imaging circuit analysis [CMOS IC latchup]","authors":"F. Stellari, A. Weger, P. Song, M. McManus","doi":"10.1109/ESSDER.2004.1356525","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356525","url":null,"abstract":"In this work, we present a methodology based on the combination of transmission line pulse (TLP) stimulation and picosecond imaging circuit analysis (PICA) for studying the dynamic onset of latchup. A mathematical model, based on carrier recombination equations, is also discussed and is shown to be in very good agreement with experimental data.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124529080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High frequency characteristics of MOSFETs with compact waffle layout 紧凑华夫饼结构的mosfet高频特性
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356569
Wen Wu, S. Lam, P. Ko, M. Chan
{"title":"High frequency characteristics of MOSFETs with compact waffle layout","authors":"Wen Wu, S. Lam, P. Ko, M. Chan","doi":"10.1109/ESSDER.2004.1356569","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356569","url":null,"abstract":"The high frequency characteristics of waffle MOSFETs are studied. In addition to area saving, the waffle MOSFETs also provide enhancement of the RF characteristics. When compared with the conventional multi-finger layout with the same device width, the waffle MOSFETs provide extra flexibility in the design window. Measured S-parameters from a 0.35 /spl mu/m technology process, over a wide range of bias conditions, indicate that the waffle MOSFET is capable of offering enhancements in f/sub max/, f/sub T/, and minimum noise figure, with careful design.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125084062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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