Low temperature process flow optimisation for 65nm CMOS mixed-signal applications

Abstract

In this work, a complete low temperature 65 nm process flow using a low-cost, conventional CMOS approach has been investigated. A significant global thermal budget reduction has been achieved (below 500/spl deg/C), especially for the spacer, silicide-protection and salicide modules. The introduction of new materials induced a great transistor performance enhancement in both the digital and analog/mixed-signal domains. The I/sub off/-I/sub on/ figure of merit has been improved by 20%, whereas the matching factors were reduced for both NMOS and PMOS transistors. This new optimized process flow satisfies the strict criteria of transistor reliability.