嵌入式应用的相变存储器技术

F. Ottogalli, A. Pirovano, F. Pellizzer, M. Tosi, P. Zuliani, P. Bonetalli, R. Bez
{"title":"嵌入式应用的相变存储器技术","authors":"F. Ottogalli, A. Pirovano, F. Pellizzer, M. Tosi, P. Zuliani, P. Bonetalli, R. Bez","doi":"10.1109/ESSDER.2004.1356547","DOIUrl":null,"url":null,"abstract":"A novel p-trench phase-change memory (PCM) cell and its integration with a MOSFET selector in a standard 0.18 /spl mu/m CMOS technology are presented. The high-performance capabilities of PCM cells are experimentally investigated and their application in embedded systems is discussed. Write times as low as 10 ns and 20 ns have been measured for the RESET and SET operation, respectively, still granting a 10/spl times/ read margin. The impact of the RESET pulse on PCH cell endurance has been also evaluated. Finally, cell distributions and first statistical endurance measurements on a 4 Mbit MOS demonstrator clearly assess the feasibility of the PCM technology.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"36","resultStr":"{\"title\":\"Phase-change memory technology for embedded applications\",\"authors\":\"F. Ottogalli, A. Pirovano, F. Pellizzer, M. Tosi, P. Zuliani, P. Bonetalli, R. Bez\",\"doi\":\"10.1109/ESSDER.2004.1356547\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel p-trench phase-change memory (PCM) cell and its integration with a MOSFET selector in a standard 0.18 /spl mu/m CMOS technology are presented. The high-performance capabilities of PCM cells are experimentally investigated and their application in embedded systems is discussed. Write times as low as 10 ns and 20 ns have been measured for the RESET and SET operation, respectively, still granting a 10/spl times/ read margin. The impact of the RESET pulse on PCH cell endurance has been also evaluated. Finally, cell distributions and first statistical endurance measurements on a 4 Mbit MOS demonstrator clearly assess the feasibility of the PCM technology.\",\"PeriodicalId\":287103,\"journal\":{\"name\":\"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-11-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"36\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDER.2004.1356547\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDER.2004.1356547","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 36

摘要

提出了一种新型的p沟槽相变存储器(PCM)单元,并将其与MOSFET选择器集成在标准的0.18 /spl mu/m CMOS技术中。实验研究了PCM单元的高性能性能,并讨论了其在嵌入式系统中的应用。对于RESET和SET操作,分别测量到低至10 ns和20 ns的写入时间,仍然授予10/spl次/读余量。RESET脉冲对PCH细胞耐力的影响也被评估。最后,在4 Mbit MOS演示器上进行的单元分布和首次统计持久测量清楚地评估了PCM技术的可行性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Phase-change memory technology for embedded applications
A novel p-trench phase-change memory (PCM) cell and its integration with a MOSFET selector in a standard 0.18 /spl mu/m CMOS technology are presented. The high-performance capabilities of PCM cells are experimentally investigated and their application in embedded systems is discussed. Write times as low as 10 ns and 20 ns have been measured for the RESET and SET operation, respectively, still granting a 10/spl times/ read margin. The impact of the RESET pulse on PCH cell endurance has been also evaluated. Finally, cell distributions and first statistical endurance measurements on a 4 Mbit MOS demonstrator clearly assess the feasibility of the PCM technology.
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