新颖的三维46F/sup 2/ SRAM技术，采用0.294um/sup 2/ S/sup 3/(堆叠单晶Si)电池和SSTFT(堆叠单晶薄膜晶体管)

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI:10.1109/ESSDER.2004.1356587

J.H. Jang, S. Jung, Y.H. Kang, W.S. Cho, J.H. Moon, C. Yeo, K. Kwak, B.H. Choi, B. Hwang, W. Jung, S. Kim, J. Kim, J. Na, H. Lim, J. Jeong, Kinam Kim

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引用次数: 0

摘要

我们采用80纳米技术和单栈S/sup 3/ cell技术实现了46F/sup 2/ SRAM单元尺寸为0.294 /spl mu/m/sup 2/。SSTFTs和垂直节点触点是S/sup 3/ cell技术的关键。研制了用于S/sup 3/ SRAM单元负载pMOS SSTFT的叠层单晶硅薄膜。负载pMOS SSTFT堆叠在ILD上以减小SRAM单元大小。完全工作的64 Mbit SRAM是通过S/sup 3/ cell技术实现的。本文还研究了长度为80 nm的SSTFT的基本可靠性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Novel 3-dimensional 46F/sup 2/ SRAM technology with 0.294um/sup 2/ S/sup 3/ (stacked single-crystal Si) cell and SSTFT (stacked single-crystal thin film transistor)

We have realized a 46F/sup 2/ SRAM cell size of 0.294 /spl mu/m/sup 2/ with 80 nm technology and single stack S/sup 3/ cell technology. SSTFTs and vertical node contacts are major keys in the S/sup 3/ cell technology. The stacked single crystal silicon thin film is developed for the load pMOS SSTFT of the S/sup 3/ SRAM cell. The load pMOS SSTFT is stacked on ILD to reduce the SRAM cell size. Fully working 64 Mbit SRAM is achieved by this S/sup 3/ cell technology. The basic reliability of SSTFT, with 80 nm length, is also investigated in this study.

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Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)

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