Novel 3-dimensional 46F/sup 2/ SRAM technology with 0.294um/sup 2/ S/sup 3/ (stacked single-crystal Si) cell and SSTFT (stacked single-crystal thin film transistor)

Abstract

We have realized a 46F/sup 2/ SRAM cell size of 0.294 /spl mu/m/sup 2/ with 80 nm technology and single stack S/sup 3/ cell technology. SSTFTs and vertical node contacts are major keys in the S/sup 3/ cell technology. The stacked single crystal silicon thin film is developed for the load pMOS SSTFT of the S/sup 3/ SRAM cell. The load pMOS SSTFT is stacked on ILD to reduce the SRAM cell size. Fully working 64 Mbit SRAM is achieved by this S/sup 3/ cell technology. The basic reliability of SSTFT, with 80 nm length, is also investigated in this study.