FinFET SRAM for high-performance low-power applications

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI:10.1109/ESSDER.2004.1356490

R. Joshi, R.Q. Williams, E. Nowak, K. Kim, J. Beintner, T. Ludwig, I. Aller, C. Chuang

引用次数: 49

Abstract

The SRAM behavior of FinFET technology is investigated and compared with 90 nm node planar partially-depleted silicon-on-insulator (PD-SOI) technology. Unique FinFET circuit behavior in SRAM applications, resulting from the near-ideal device characteristics, is demonstrated by full cell cross section simulation for the first time, and shows high performance and low active and standby power. SRAM stability is analyzed in detail, as compared to PD-SOI.

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用于高性能低功耗应用的FinFET SRAM

研究了FinFET技术的SRAM性能，并与90 nm节点平面部分耗尽绝缘体上硅(PD-SOI)技术进行了比较。在SRAM应用中独特的FinFET电路行为，源于近乎理想的器件特性，首次通过全单元截面模拟得到证明，并显示出高性能和低主动式和待机功率。与PD-SOI相比，详细分析了SRAM的稳定性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)

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