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Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)最新文献

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Low voltage (1.2V) and high performance mobile DRAM device technology with dual poly-silicon gate using plasma nitrided gate oxide 低电压(1.2V)和高性能移动DRAM器件技术与双多晶硅栅极采用等离子体氮化栅极氧化物
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356586
S. Hong, B. Koo, T. Jeon, S. Hyun, Y. Shin, U. Chung, J. Moon
{"title":"Low voltage (1.2V) and high performance mobile DRAM device technology with dual poly-silicon gate using plasma nitrided gate oxide","authors":"S. Hong, B. Koo, T. Jeon, S. Hyun, Y. Shin, U. Chung, J. Moon","doi":"10.1109/ESSDER.2004.1356586","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356586","url":null,"abstract":"The plasma nitrided gate oxide process has been developed and applied for mobile DRAM with low operating voltage. As a result, we confirm that plasma nitrided gate oxide can block the boron penetration in DRAM, which has a higher thermal budget than other devices. The nitrogen bonding status and profile are investigated to check the change in transistor and gate oxide characteristics.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"235 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124582999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
101 GHz f/sub Tmax/ SiGe:C HBT integrated into 0.25 /spl mu/m CMOS with conventional LOCOS isolation 101 GHz f/sub Tmax/ SiGe:C HBT集成到0.25 /spl mu/m CMOS中，采用传统的LOCOS隔离
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356524
H. Yamagata, S. Yanagawa, T. Komoto, M. Bairo, Y. Kiyota, S. Yoneda, M. Oishi, A. Kuranouchi, C. Arai
{"title":"101 GHz f/sub Tmax/ SiGe:C HBT integrated into 0.25 /spl mu/m CMOS with conventional LOCOS isolation","authors":"H. Yamagata, S. Yanagawa, T. Komoto, M. Bairo, Y. Kiyota, S. Yoneda, M. Oishi, A. Kuranouchi, C. Arai","doi":"10.1109/ESSDER.2004.1356524","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356524","url":null,"abstract":"A low-complexity but high-performance SiGe:C BiCMOS technology is realized by conventional simple LOCOS isolation and non-selective SiGe:C epitaxy with optimized impurity profiles. Stress-induced misfit dislocations found in the SiGe:C layer on LOCOS-patterned wafers were successfully eliminated by optimizing the epitaxial process. This, in combination with optimization of HBT impurity profiles, produced a 99% yield of 10000 parallel arrays with an f/sub Tmax/ of 101 GHz. The HBT has been successfully integrate in a 0.25 /spl mu/m CMOS with passive components, which is suitable for low-cost RF mixed-signal applications.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128018864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A two mask complementary LDMOS module integrated in a 0.25 /spl mu/m SiGe:C BiCMOS platform 一个双掩模互补的LDMOS模块集成在0.25 /spl mu/m SiGe:C BiCMOS平台上
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356503
K. Ehwald, A. Fischer, F. Fuernhammer, W. Winkler, B. Senapati, R. Barth, D. Bolze, B. Heinemann, D. Knoll, H. Ruecker, D. Schmidt, I. Shevchenko, R. Sorge, H. Wulf
{"title":"A two mask complementary LDMOS module integrated in a 0.25 /spl mu/m SiGe:C BiCMOS platform","authors":"K. Ehwald, A. Fischer, F. Fuernhammer, W. Winkler, B. Senapati, R. Barth, D. Bolze, B. Heinemann, D. Knoll, H. Ruecker, D. Schmidt, I. Shevchenko, R. Sorge, H. Wulf","doi":"10.1109/ESSDER.2004.1356503","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356503","url":null,"abstract":"The integration of RF n-and p-LDMOS transistors into a CMOS or BiCMOS platform allows the use of complementary circuit techniques and enables efficient solutions for linear RF power amplifiers, power switches, DC/DC converters and high voltage IO circuits. We demonstrate the modular integration of high performance n-LDMOS devices and a record p-LDMOS transistor into a low-cost 0.25 /spl mu/m SiGe:C RF-BiCMOS technology. In addition to n-LDMOS transistors on a p-substrate with breakdown voltages near 30 V, isolated n-LDMOS- and p-LDMOS transistors can be manufactured on the same wafer and achieve breakdown voltages of 11.5 V and 13.5 V and f/sub T//f/sub max/ values of 23/48 GHz or 13/30 GHz, respectively.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115970634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Self-aligned access gate technology for compact embedded flash memories 紧凑型嵌入式快闪记忆体的自对准存取门技术
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356544
P. Goarin, R. van Schaijk, M. Slotboom, P. Tello, M. van Duuren, N. Akil, W. Baks
{"title":"Self-aligned access gate technology for compact embedded flash memories","authors":"P. Goarin, R. van Schaijk, M. Slotboom, P. Tello, M. van Duuren, N. Akil, W. Baks","doi":"10.1109/ESSDER.2004.1356544","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356544","url":null,"abstract":"This paper investigates an approach to solve the access gate misalignment issues linked to the poly-CMP process of compact cells. The process of this self-aligned access gate approach is be detailed and measurements demonstrate the viability of this approach and show that the issues associated with access gate misalignment, such as parameter spread among cells during source side injection programming, are gone. This paves the way for aggressively scaled low power embedded nonvolatile memories for the next CMOS generations.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"37 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116425545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impact of thermal overload operation on wirebond and metallization reliability in smart power devices 智能电力设备中热过载运行对焊丝和金属化可靠性的影响
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356542
M. Glavanovics, T. Detzel, K. Weber
{"title":"Impact of thermal overload operation on wirebond and metallization reliability in smart power devices","authors":"M. Glavanovics, T. Detzel, K. Weber","doi":"10.1109/ESSDER.2004.1356542","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356542","url":null,"abstract":"It is well-known that continuous operation of semiconductors under electrical and thermal overload conditions leads to degradation and subsequently to device failure. This paper deals with wirebond and metallization degradation of integrated vertical DMOS switches that are stressed with periodic power dissipation pulses under laboratory conditions. The test setup is briefly described as well as the test results. Physical failure analysis proves that migration phenomena in the power metallization, as well as bond wire delamination, play a crucial role in device aging. A model of time to failure is derived from measured data. It implies that thermomechanical as well as electrical mechanisms contribute to final device failure. Several hypotheses are discussed, showing that the wirebond-metallization interface is most probably the weak point of power switch robustness. Further tasks will therefore include evaluating possible improvements on power metallization and bond connection reliability.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115689890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Integration of photonic functions in and with silicon 光子函数在硅中的积分和与硅的积分
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356486
R. Baets, W. Bogaerts, P. Dumon, G. Roelkens, I. Christiaens, K. De Mesel, D. Taillaert, B. Luyssaert, J. Van Campenhout, P. Bienstman, D. van Thourhout, V. Wiaux, J. Wouters, S. Beckx
{"title":"Integration of photonic functions in and with silicon","authors":"R. Baets, W. Bogaerts, P. Dumon, G. Roelkens, I. Christiaens, K. De Mesel, D. Taillaert, B. Luyssaert, J. Van Campenhout, P. Bienstman, D. van Thourhout, V. Wiaux, J. Wouters, S. Beckx","doi":"10.1109/ESSDER.2004.1356486","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356486","url":null,"abstract":"Silicon is gaining importance in photonic systems on a chip, either because of the importance of integrating photonic functions with electronic functions or because of the potential of silicon-based technology for photonics as such. In this paper, we discuss two distinct developments. The first is the development of nano-photonic integrated circuits based on photonic crystals or photonic wires. The second is the development of heterogeneously integrated active photonic components on top of silicon by means of wafer bonding.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121598914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Back-gated SOI technology: power-adaptive logic and non-volatile memory using identical processing 反向门控SOI技术:功率自适应逻辑和使用相同处理的非易失性存储器
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356545
U. Avci, A. Kumar, Haitao Liu, S. Tiwari
{"title":"Back-gated SOI technology: power-adaptive logic and non-volatile memory using identical processing","authors":"U. Avci, A. Kumar, Haitao Liu, S. Tiwari","doi":"10.1109/ESSDER.2004.1356545","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356545","url":null,"abstract":"A back-gated scalable silicon-on-insulator (SOI) technology that provides a non-volatile memory, logic with adaptive power-performance trade-off and buried interconnectivity is reported. The back-gate approach has the following characteristics: (1) a logic transistor whose threshold voltage modulation allows adaptive power control of digital and analog circuits, (2) a non-volatile memory where the read-transistor scaling is decoupled from storage constraints, (3) good SOI thickness control, (4) speed degradation due to alignment tolerances lower than 16%, (5) a new analog design approach to achieve adaptive low voltage operation within digital constraints.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124622072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Influence of an accumulation back-gate voltage on the low-frequency noise spectra of 0.13 /spl mu/m fully-depleted SOI MOSFETs fabricated on ELTRAN and UNIBOND wafers 累积后极电压对ELTRAN和UNIBOND晶圆上0.13 /spl mu/m全耗尽SOI mosfet低频噪声谱的影响
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356563
N. Litkyanchikova, N. Garbar, A. Smolanka, E. Simoen, C. Claeys
{"title":"Influence of an accumulation back-gate voltage on the low-frequency noise spectra of 0.13 /spl mu/m fully-depleted SOI MOSFETs fabricated on ELTRAN and UNIBOND wafers","authors":"N. Litkyanchikova, N. Garbar, A. Smolanka, E. Simoen, C. Claeys","doi":"10.1109/ESSDER.2004.1356563","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356563","url":null,"abstract":"The behaviour of so-called back-gate induced Lorentzians has been investigated in fully depleted (FD) silicon-on-insulator (SOI) MOSFETs, fabricated in a 0.13 /spl mu/m CMOS technology, on ELTRAN and UNIBOND wafers. While this excess low-frequency (LF) noise source is fairly easily observed in ELTRAN (E) p-and UNIBOND (U) nMOSFETs, when the back-gate voltage (V/sub GB/) is in accumulation, this is not true for their n-(E) and p-channel (U) counterparts. It is be demonstrated that the origin of this novel noise source resembles the one of the electron valence band (EVB) tunnelling related Lorentzians, although it occurs at front-gate voltages below the EVB tunnelling threshold. It is shown that in this case, the RC-filtered Nyquist noise of the source and drain junctions at the back interface is the main cause of the excess Lorentzians.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120939035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Magnetoresistance mobility measurements in sub 0.1 /spl mu/m Si MOSFETs 低于0.1 /spl mu/m Si mosfet的磁阻迁移率测量
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356513
Y. Meziani, J. Lusakowski, F. Teppe, N. Dyakonova, W. Knap, K. Romanjek, M. Ferrier, R. Clerc, G. Ghibaudo, F. Boeuf, T. Skotnicki
{"title":"Magnetoresistance mobility measurements in sub 0.1 /spl mu/m Si MOSFETs","authors":"Y. Meziani, J. Lusakowski, F. Teppe, N. Dyakonova, W. Knap, K. Romanjek, M. Ferrier, R. Clerc, G. Ghibaudo, F. Boeuf, T. Skotnicki","doi":"10.1109/ESSDER.2004.1356513","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356513","url":null,"abstract":"In this work, for the first time, are reported magnetoresistance (MR) mobility measurements performed on sub 0.1 /spl mu/m Si MOSFETs. This method enables the carrier mobility to be measured from weak to strong inversion without knowing the device channel length. The MR mobility results are compared to effective mobility data obtained by standard parameter extraction and split C-V techniques. The MR data clearly indicates a significant decrease of the mobility with the gate length reduction. This behavior and the difference between MR and effective mobility values are discussed and interpreted by 2D transport analysis.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131226023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Ge-on-Si pin-photodiodes for vertical and in-plane detection of 1300 to 1580 nm light Ge-on-Si针脚光电二极管用于1300至1580 nm光的垂直和面内检测
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI: 10.1109/ESSDER.2004.1356560
M. Jutzi, M. Berroth, G. Wohl, M. Oehme, V. Stefani, E. Kasper
{"title":"Ge-on-Si pin-photodiodes for vertical and in-plane detection of 1300 to 1580 nm light","authors":"M. Jutzi, M. Berroth, G. Wohl, M. Oehme, V. Stefani, E. Kasper","doi":"10.1109/ESSDER.2004.1356560","DOIUrl":"https://doi.org/10.1109/ESSDER.2004.1356560","url":null,"abstract":"Ge-on-Si pin-photodiodes for vertical and in-plane detection are presented. The devices are grown on an 31 nm ultrathin, strain relaxed buffer (SRB) layer. The vertical photodiode exhibits a zero-bias responsivity of 117 mA/W and a bandwidth of 1.5 GHz at a wavelength of 1298 nm. In comparison, the detector for in-plane detection has a zero-bias responsivity of 70 mA/W and a bandwidth of 4.4 GHz. For a bias voltage of -2 V a bandwidth of 6.2 GHz has been measured. At 1580 nm the photo responsivity of the lateral photodiode is higher (26 mA/W) than of the vertical photodiode (19 mA/W). The dislocation density probably may limit the bandwidth.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132193326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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