101 GHz f/sub Tmax/ SiGe:C HBT集成到0.25 /spl mu/m CMOS中，采用传统的LOCOS隔离

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI:10.1109/ESSDER.2004.1356524

H. Yamagata, S. Yanagawa, T. Komoto, M. Bairo, Y. Kiyota, S. Yoneda, M. Oishi, A. Kuranouchi, C. Arai

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引用次数: 0

摘要

通过传统的简单LOCOS隔离和优化杂质谱的非选择性SiGe:C外延，实现了低复杂度、高性能的SiGe:C BiCMOS技术。通过优化外延工艺，成功地消除了locos晶圆上SiGe:C层应力引起的错配位错。这与HBT杂质谱的优化相结合，产生了99%的产率，10000个并行阵列，f/sub Tmax/为101 GHz。HBT已成功集成在0.25 /spl mu/m CMOS中，具有无源元件，适用于低成本射频混合信号应用。

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101 GHz f/sub Tmax/ SiGe:C HBT integrated into 0.25 /spl mu/m CMOS with conventional LOCOS isolation

A low-complexity but high-performance SiGe:C BiCMOS technology is realized by conventional simple LOCOS isolation and non-selective SiGe:C epitaxy with optimized impurity profiles. Stress-induced misfit dislocations found in the SiGe:C layer on LOCOS-patterned wafers were successfully eliminated by optimizing the epitaxial process. This, in combination with optimization of HBT impurity profiles, produced a 99% yield of 10000 parallel arrays with an f/sub Tmax/ of 101 GHz. The HBT has been successfully integrate in a 0.25 /spl mu/m CMOS with passive components, which is suitable for low-cost RF mixed-signal applications.

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Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)

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