Optimized cell structure for FinFET array Flash memory

Abstract

In this paper, a highly manufacturable 256 M body tied tri-gate fin array NOR-type Flash memory, with 70 nm fin width, was successfully fabricated and the characteristics were compared with planar cell array transistors. In this experiment, a 1.6 times higher driving current of the fin array flash memory cell transistor is achieved than that of a planar device with the same gate length. We propose an optimized fin structure for flash memory operation and a direction for enhanced current of the fin array flash memory cell transistor with respect to the channel silicon plane, coupling ratio, junction profile and anti-punch through implantation conditions.